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The GICv3 code has always supported a configurable number of virtual priority and preemption bits, but our implementation currently hardcodes the number of physical priority bits at 8. This is not what most hardware implementations provide; for instance the Cortex-A53 provides only 5 bits of physical priority. Make the number of physical priority/preemption bits driven by fields in the GICv3CPUState, the way that we already do for virtual priority/preemption bits. We set cs->pribits to 8, so there is no behavioural change in this commit. A following commit will add the machinery for CPUs to set this to the correct value for their implementation. Note that changing the number of priority bits would be a migration compatibility break, because the semantics of the icc_apr[][] array changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220512151457.3899052-5-peter.maydell@linaro.org Message-id: 20220506162129.2896966-4-peter.maydell@linaro.org |
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| .. | ||
| allwinner-a10-pic.h | ||
| arm_gic_common.h | ||
| arm_gic.h | ||
| arm_gicv3_common.h | ||
| arm_gicv3_its_common.h | ||
| arm_gicv3.h | ||
| armv7m_nvic.h | ||
| aspeed_vic.h | ||
| bcm2835_ic.h | ||
| bcm2836_control.h | ||
| exynos4210_combiner.h | ||
| exynos4210_gic.h | ||
| goldfish_pic.h | ||
| heathrow_pic.h | ||
| i8259.h | ||
| imx_avic.h | ||
| imx_gpcv2.h | ||
| intc.h | ||
| loongson_liointc.h | ||
| m68k_irqc.h | ||
| mips_gic.h | ||
| nios2_vic.h | ||
| ppc-uic.h | ||
| realview_gic.h | ||
| riscv_aclint.h | ||
| riscv_aplic.h | ||
| riscv_imsic.h | ||
| rx_icu.h | ||
| sifive_plic.h | ||
| xlnx-pmu-iomod-intc.h | ||
| xlnx-zynqmp-ipi.h | ||