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762e22edcd
Note that the specification for lf.madd.s is confused. It's the only mention of supposed FPMADDHI/FPMADDLO special registers. On the other hand, or1ksim implements a somewhat normal non-fused multiply and add. Mirror that. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
282 lines
12 KiB
C
282 lines
12 KiB
C
/*
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* OpenRISC float helper routines
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Feng Gao <gf91597@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exception.h"
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static inline uint32_t ieee_ex_to_openrisc(OpenRISCCPU *cpu, int fexcp)
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{
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int ret = 0;
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if (fexcp) {
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if (fexcp & float_flag_invalid) {
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cpu->env.fpcsr |= FPCSR_IVF;
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ret = 1;
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}
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if (fexcp & float_flag_overflow) {
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cpu->env.fpcsr |= FPCSR_OVF;
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ret = 1;
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}
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if (fexcp & float_flag_underflow) {
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cpu->env.fpcsr |= FPCSR_UNF;
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ret = 1;
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}
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if (fexcp & float_flag_divbyzero) {
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cpu->env.fpcsr |= FPCSR_DZF;
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ret = 1;
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}
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if (fexcp & float_flag_inexact) {
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cpu->env.fpcsr |= FPCSR_IXF;
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ret = 1;
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}
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}
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return ret;
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}
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static inline void update_fpcsr(OpenRISCCPU *cpu)
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{
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int tmp = ieee_ex_to_openrisc(cpu,
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get_float_exception_flags(&cpu->env.fp_status));
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SET_FP_CAUSE(cpu->env.fpcsr, tmp);
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if ((GET_FP_ENABLE(cpu->env.fpcsr) & tmp) &&
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(cpu->env.fpcsr & FPCSR_FPEE)) {
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helper_exception(&cpu->env, EXCP_FPE);
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} else {
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UPDATE_FP_FLAGS(cpu->env.fpcsr, tmp);
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}
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}
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uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
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{
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uint64_t itofd;
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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set_float_exception_flags(0, &cpu->env.fp_status);
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itofd = int32_to_float64(val, &cpu->env.fp_status);
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update_fpcsr(cpu);
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return itofd;
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}
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uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val)
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{
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uint32_t itofs;
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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set_float_exception_flags(0, &cpu->env.fp_status);
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itofs = int32_to_float32(val, &cpu->env.fp_status);
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update_fpcsr(cpu);
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return itofs;
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}
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uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val)
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{
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uint64_t ftoid;
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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set_float_exception_flags(0, &cpu->env.fp_status);
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ftoid = float32_to_int64(val, &cpu->env.fp_status);
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update_fpcsr(cpu);
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return ftoid;
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}
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uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val)
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{
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uint32_t ftois;
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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set_float_exception_flags(0, &cpu->env.fp_status);
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ftois = float32_to_int32(val, &cpu->env.fp_status);
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update_fpcsr(cpu);
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return ftois;
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}
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#define FLOAT_OP(name, p) void helper_float_##_##p(void)
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#define FLOAT_CALC(name) \
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uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
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uint64_t fdt0, uint64_t fdt1) \
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{ \
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uint64_t result; \
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
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set_float_exception_flags(0, &cpu->env.fp_status); \
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result = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
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update_fpcsr(cpu); \
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return result; \
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} \
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\
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uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
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uint32_t fdt0, uint32_t fdt1) \
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{ \
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uint32_t result; \
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
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set_float_exception_flags(0, &cpu->env.fp_status); \
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result = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
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update_fpcsr(cpu); \
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return result; \
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} \
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FLOAT_CALC(add)
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FLOAT_CALC(sub)
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FLOAT_CALC(mul)
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FLOAT_CALC(div)
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FLOAT_CALC(rem)
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#undef FLOAT_CALC
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uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a,
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uint64_t b, uint64_t c)
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{
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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uint64_t result;
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set_float_exception_flags(0, &cpu->env.fp_status);
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/* Note that or1ksim doesn't use merged operation. */
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result = float64_mul(b, c, &cpu->env.fp_status);
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result = float64_add(result, a, &cpu->env.fp_status);
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update_fpcsr(cpu);
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return result;
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}
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uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a,
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uint32_t b, uint32_t c)
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{
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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uint32_t result;
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set_float_exception_flags(0, &cpu->env.fp_status);
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/* Note that or1ksim doesn't use merged operation. */
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result = float32_mul(b, c, &cpu->env.fp_status);
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result = float32_add(result, a, &cpu->env.fp_status);
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update_fpcsr(cpu);
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return result;
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}
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#define FLOAT_CMP(name) \
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uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
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uint64_t fdt0, uint64_t fdt1) \
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{ \
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int res; \
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
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set_float_exception_flags(0, &cpu->env.fp_status); \
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res = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
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update_fpcsr(cpu); \
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return res; \
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} \
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\
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uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
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uint32_t fdt0, uint32_t fdt1)\
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{ \
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int res; \
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
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set_float_exception_flags(0, &cpu->env.fp_status); \
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res = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \
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update_fpcsr(cpu); \
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return res; \
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}
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FLOAT_CMP(le)
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FLOAT_CMP(eq)
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FLOAT_CMP(lt)
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#undef FLOAT_CMP
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#define FLOAT_CMPNE(name) \
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uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
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uint64_t fdt0, uint64_t fdt1) \
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{ \
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int res; \
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
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set_float_exception_flags(0, &cpu->env.fp_status); \
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res = !float64_eq_quiet(fdt0, fdt1, &cpu->env.fp_status); \
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update_fpcsr(cpu); \
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return res; \
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} \
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\
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uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
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uint32_t fdt0, uint32_t fdt1) \
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{ \
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int res; \
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
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set_float_exception_flags(0, &cpu->env.fp_status); \
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res = !float32_eq_quiet(fdt0, fdt1, &cpu->env.fp_status); \
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update_fpcsr(cpu); \
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return res; \
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}
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FLOAT_CMPNE(ne)
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#undef FLOAT_CMPNE
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#define FLOAT_CMPGT(name) \
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uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
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uint64_t fdt0, uint64_t fdt1) \
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{ \
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int res; \
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
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set_float_exception_flags(0, &cpu->env.fp_status); \
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res = !float64_le(fdt0, fdt1, &cpu->env.fp_status); \
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update_fpcsr(cpu); \
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return res; \
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} \
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\
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uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
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uint32_t fdt0, uint32_t fdt1) \
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{ \
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int res; \
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
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set_float_exception_flags(0, &cpu->env.fp_status); \
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res = !float32_le(fdt0, fdt1, &cpu->env.fp_status); \
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update_fpcsr(cpu); \
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return res; \
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}
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FLOAT_CMPGT(gt)
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#undef FLOAT_CMPGT
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#define FLOAT_CMPGE(name) \
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uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
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uint64_t fdt0, uint64_t fdt1) \
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{ \
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int res; \
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
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set_float_exception_flags(0, &cpu->env.fp_status); \
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res = !float64_lt(fdt0, fdt1, &cpu->env.fp_status); \
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update_fpcsr(cpu); \
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return res; \
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} \
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\
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uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
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uint32_t fdt0, uint32_t fdt1) \
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{ \
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int res; \
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \
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set_float_exception_flags(0, &cpu->env.fp_status); \
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res = !float32_lt(fdt0, fdt1, &cpu->env.fp_status); \
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update_fpcsr(cpu); \
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return res; \
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}
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FLOAT_CMPGE(ge)
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#undef FLOAT_CMPGE
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