Alex Bennée 864df2058d target/arm64: properly handle DBGVR RESS bits ...

This only fails with some (broken) versions of gdb but we should
treat the top bits of DBGBVR as RESS. Properly sign extend QEMU's
reference copy of dbgbvr and also update the register descriptions in
the comment.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181109152119.9242-2-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2018-11-13 10:47:59 +00:00

..

alpha

target/alpha: remove tlb_flush from alpha_cpu_initfn

2018-10-18 18:58:10 -07:00

arm

target/arm64: properly handle DBGVR RESS bits

2018-11-13 10:47:59 +00:00

cris

target/cris/translate: Get rid of qemu_log_separate()

2018-10-16 17:57:23 +02:00

hppa

target/hppa: Raise exception 26 on emulated hardware

2018-10-16 15:32:22 -07:00

i386

target/i386: Clear RF on SYSCALL instruction

2018-11-06 21:35:05 +01:00

lm32

tcg-next queue

2018-06-04 11:28:31 +01:00

m68k

target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTED

2018-11-01 12:12:24 +01:00

microblaze

target-microblaze: Rework NOP/zero instruction handling

2018-06-15 09:05:00 +02:00

mips

target/mips: Amend MXU ASE overview note

2018-10-29 14:13:59 +01:00

moxie

tcg-next queue

2018-06-04 11:28:31 +01:00

nios2

tcg-next queue

2018-06-04 11:28:31 +01:00

openrisc

decodetree: Remove "insn" argument from trans_* expanders

2018-10-31 16:48:54 +00:00

ppc

ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HV

2018-11-08 13:08:35 +11:00

riscv

target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

2018-10-30 11:04:28 -07:00

s390x

target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate

2018-10-18 19:46:53 -07:00

sh4

sh4: fix use_icount with linux-user

2018-08-20 00:11:06 +02:00

sparc

SPARC64: add icount support

2018-06-17 11:13:06 +01:00

tilegx

tcg-next queue

2018-06-04 11:28:31 +01:00

tricore

tcg: Pass tb and index to tcg_gen_exit_tb separately

2018-06-01 15:15:27 -07:00

unicore32

target/unicore32: remove tlb_flush from uc32_init_fn

2018-10-18 18:58:10 -07:00

xtensa

target/xtensa: extract gen_check_interrupts call

2018-10-01 11:08:36 -07:00