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a78e9839ae
Add an asynchronous version of i2c_send() that requires the slave to explicitly acknowledge on the bus with i2c_ack(). The current master must use the new i2c_start_send_async() to indicate that it wants to do an asynchronous transfer. This allows the i2c core to check if the target slave supports this or not. This approach relies on adding a new enum i2c_event member, which is why a bunch of other devices needs changes in their event handling switches. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Message-Id: <20220601210831.67259-5-its@irrelevant.dk> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-6-me@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
424 lines
10 KiB
C
424 lines
10 KiB
C
/*
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* QEMU I2C bus interface.
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the LGPL.
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*/
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#include "qemu/osdep.h"
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#include "hw/i2c/i2c.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "qemu/main-loop.h"
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#include "trace.h"
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#define I2C_BROADCAST 0x00
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static Property i2c_props[] = {
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DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static const TypeInfo i2c_bus_info = {
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.name = TYPE_I2C_BUS,
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.parent = TYPE_BUS,
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.instance_size = sizeof(I2CBus),
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};
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static int i2c_bus_pre_save(void *opaque)
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{
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I2CBus *bus = opaque;
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bus->saved_address = -1;
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if (!QLIST_EMPTY(&bus->current_devs)) {
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if (!bus->broadcast) {
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bus->saved_address = QLIST_FIRST(&bus->current_devs)->elt->address;
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} else {
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bus->saved_address = I2C_BROADCAST;
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}
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}
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return 0;
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}
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static const VMStateDescription vmstate_i2c_bus = {
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.name = "i2c_bus",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = i2c_bus_pre_save,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(saved_address, I2CBus),
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VMSTATE_END_OF_LIST()
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}
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};
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/* Create a new I2C bus. */
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I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
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{
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I2CBus *bus;
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bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name));
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QLIST_INIT(&bus->current_devs);
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QSIMPLEQ_INIT(&bus->pending_masters);
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vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_i2c_bus, bus);
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return bus;
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}
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void i2c_slave_set_address(I2CSlave *dev, uint8_t address)
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{
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dev->address = address;
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}
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/* Return nonzero if bus is busy. */
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int i2c_bus_busy(I2CBus *bus)
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{
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return !QLIST_EMPTY(&bus->current_devs) || bus->bh;
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}
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bool i2c_scan_bus(I2CBus *bus, uint8_t address, bool broadcast,
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I2CNodeList *current_devs)
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{
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BusChild *kid;
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QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
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DeviceState *qdev = kid->child;
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I2CSlave *candidate = I2C_SLAVE(qdev);
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I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(candidate);
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if (sc->match_and_add(candidate, address, broadcast, current_devs)) {
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if (!broadcast) {
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return true;
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}
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}
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}
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/*
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* If broadcast was true, and the list was full or empty, return true. If
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* broadcast was false, return false.
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*/
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return broadcast;
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}
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/* TODO: Make this handle multiple masters. */
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/*
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* Start or continue an i2c transaction. When this is called for the
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* first time or after an i2c_end_transfer(), if it returns an error
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* the bus transaction is terminated (or really never started). If
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* this is called after another i2c_start_transfer() without an
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* intervening i2c_end_transfer(), and it returns an error, the
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* transaction will not be terminated. The caller must do it.
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*
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* This corresponds with the way real hardware works. The SMBus
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* protocol uses a start transfer to switch from write to read mode
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* without releasing the bus. If that fails, the bus is still
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* in a transaction.
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*
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* @event must be I2C_START_RECV or I2C_START_SEND.
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*/
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static int i2c_do_start_transfer(I2CBus *bus, uint8_t address,
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enum i2c_event event)
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{
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I2CSlaveClass *sc;
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I2CNode *node;
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bool bus_scanned = false;
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if (address == I2C_BROADCAST) {
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/*
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* This is a broadcast, the current_devs will be all the devices of the
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* bus.
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*/
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bus->broadcast = true;
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}
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/*
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* If there are already devices in the list, that means we are in
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* the middle of a transaction and we shouldn't rescan the bus.
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*
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* This happens with any SMBus transaction, even on a pure I2C
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* device. The interface does a transaction start without
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* terminating the previous transaction.
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*/
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if (QLIST_EMPTY(&bus->current_devs)) {
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/* Disregard whether devices were found. */
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(void)i2c_scan_bus(bus, address, bus->broadcast, &bus->current_devs);
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bus_scanned = true;
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}
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if (QLIST_EMPTY(&bus->current_devs)) {
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return 1;
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}
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QLIST_FOREACH(node, &bus->current_devs, next) {
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I2CSlave *s = node->elt;
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int rv;
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sc = I2C_SLAVE_GET_CLASS(s);
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/* If the bus is already busy, assume this is a repeated
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start condition. */
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if (sc->event) {
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trace_i2c_event(event == I2C_START_SEND ? "start" : "start_async",
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s->address);
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rv = sc->event(s, event);
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if (rv && !bus->broadcast) {
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if (bus_scanned) {
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/* First call, terminate the transfer. */
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i2c_end_transfer(bus);
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}
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return rv;
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}
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}
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}
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return 0;
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}
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int i2c_start_transfer(I2CBus *bus, uint8_t address, bool is_recv)
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{
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return i2c_do_start_transfer(bus, address, is_recv
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? I2C_START_RECV
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: I2C_START_SEND);
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}
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void i2c_bus_master(I2CBus *bus, QEMUBH *bh)
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{
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if (i2c_bus_busy(bus)) {
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I2CPendingMaster *node = g_new(struct I2CPendingMaster, 1);
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node->bh = bh;
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QSIMPLEQ_INSERT_TAIL(&bus->pending_masters, node, entry);
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return;
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}
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bus->bh = bh;
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qemu_bh_schedule(bus->bh);
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}
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void i2c_bus_release(I2CBus *bus)
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{
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bus->bh = NULL;
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}
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int i2c_start_recv(I2CBus *bus, uint8_t address)
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{
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return i2c_do_start_transfer(bus, address, I2C_START_RECV);
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}
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int i2c_start_send(I2CBus *bus, uint8_t address)
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{
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return i2c_do_start_transfer(bus, address, I2C_START_SEND);
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}
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int i2c_start_send_async(I2CBus *bus, uint8_t address)
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{
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return i2c_do_start_transfer(bus, address, I2C_START_SEND_ASYNC);
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}
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void i2c_end_transfer(I2CBus *bus)
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{
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I2CSlaveClass *sc;
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I2CNode *node, *next;
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QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
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I2CSlave *s = node->elt;
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sc = I2C_SLAVE_GET_CLASS(s);
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if (sc->event) {
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trace_i2c_event("finish", s->address);
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sc->event(s, I2C_FINISH);
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}
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QLIST_REMOVE(node, next);
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g_free(node);
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}
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bus->broadcast = false;
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if (!QSIMPLEQ_EMPTY(&bus->pending_masters)) {
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I2CPendingMaster *node = QSIMPLEQ_FIRST(&bus->pending_masters);
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bus->bh = node->bh;
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QSIMPLEQ_REMOVE_HEAD(&bus->pending_masters, entry);
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g_free(node);
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qemu_bh_schedule(bus->bh);
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}
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}
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int i2c_send(I2CBus *bus, uint8_t data)
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{
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I2CSlaveClass *sc;
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I2CSlave *s;
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I2CNode *node;
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int ret = 0;
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QLIST_FOREACH(node, &bus->current_devs, next) {
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s = node->elt;
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sc = I2C_SLAVE_GET_CLASS(s);
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if (sc->send) {
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trace_i2c_send(s->address, data);
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ret = ret || sc->send(s, data);
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} else {
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ret = -1;
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}
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}
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return ret ? -1 : 0;
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}
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int i2c_send_async(I2CBus *bus, uint8_t data)
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{
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I2CNode *node = QLIST_FIRST(&bus->current_devs);
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I2CSlave *slave = node->elt;
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I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(slave);
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if (!sc->send_async) {
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return -1;
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}
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trace_i2c_send_async(slave->address, data);
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sc->send_async(slave, data);
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return 0;
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}
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uint8_t i2c_recv(I2CBus *bus)
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{
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uint8_t data = 0xff;
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I2CSlaveClass *sc;
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I2CSlave *s;
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if (!QLIST_EMPTY(&bus->current_devs) && !bus->broadcast) {
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sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(&bus->current_devs)->elt);
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if (sc->recv) {
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s = QLIST_FIRST(&bus->current_devs)->elt;
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data = sc->recv(s);
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trace_i2c_recv(s->address, data);
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}
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}
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return data;
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}
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void i2c_nack(I2CBus *bus)
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{
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I2CSlaveClass *sc;
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I2CNode *node;
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if (QLIST_EMPTY(&bus->current_devs)) {
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return;
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}
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QLIST_FOREACH(node, &bus->current_devs, next) {
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sc = I2C_SLAVE_GET_CLASS(node->elt);
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if (sc->event) {
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trace_i2c_event("nack", node->elt->address);
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sc->event(node->elt, I2C_NACK);
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}
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}
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}
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void i2c_ack(I2CBus *bus)
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{
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if (!bus->bh) {
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return;
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}
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trace_i2c_ack();
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qemu_bh_schedule(bus->bh);
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}
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static int i2c_slave_post_load(void *opaque, int version_id)
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{
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I2CSlave *dev = opaque;
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I2CBus *bus;
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I2CNode *node;
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bus = I2C_BUS(qdev_get_parent_bus(DEVICE(dev)));
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if ((bus->saved_address == dev->address) ||
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(bus->saved_address == I2C_BROADCAST)) {
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node = g_new(struct I2CNode, 1);
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node->elt = dev;
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QLIST_INSERT_HEAD(&bus->current_devs, node, next);
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}
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return 0;
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}
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const VMStateDescription vmstate_i2c_slave = {
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.name = "I2CSlave",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = i2c_slave_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(address, I2CSlave),
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VMSTATE_END_OF_LIST()
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}
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};
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I2CSlave *i2c_slave_new(const char *name, uint8_t addr)
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{
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DeviceState *dev;
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dev = qdev_new(name);
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qdev_prop_set_uint8(dev, "address", addr);
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return I2C_SLAVE(dev);
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}
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bool i2c_slave_realize_and_unref(I2CSlave *dev, I2CBus *bus, Error **errp)
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{
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return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp);
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}
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I2CSlave *i2c_slave_create_simple(I2CBus *bus, const char *name, uint8_t addr)
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{
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I2CSlave *dev = i2c_slave_new(name, addr);
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i2c_slave_realize_and_unref(dev, bus, &error_abort);
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return dev;
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}
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static bool i2c_slave_match(I2CSlave *candidate, uint8_t address,
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bool broadcast, I2CNodeList *current_devs)
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{
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if ((candidate->address == address) || (broadcast)) {
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I2CNode *node = g_new(struct I2CNode, 1);
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node->elt = candidate;
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QLIST_INSERT_HEAD(current_devs, node, next);
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return true;
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}
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/* Not found and not broadcast. */
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return false;
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}
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static void i2c_slave_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *k = DEVICE_CLASS(klass);
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I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
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set_bit(DEVICE_CATEGORY_MISC, k->categories);
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k->bus_type = TYPE_I2C_BUS;
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device_class_set_props(k, i2c_props);
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sc->match_and_add = i2c_slave_match;
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}
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static const TypeInfo i2c_slave_type_info = {
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.name = TYPE_I2C_SLAVE,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(I2CSlave),
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.abstract = true,
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.class_size = sizeof(I2CSlaveClass),
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.class_init = i2c_slave_class_init,
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};
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static void i2c_slave_register_types(void)
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{
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type_register_static(&i2c_bus_info);
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type_register_static(&i2c_slave_type_info);
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}
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type_init(i2c_slave_register_types)
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