Eduardo Habkost 885bb0369a add Opteron_G4 CPU model (v2) ... This patch addes a Bulldozer-based Opteron_G4 CPU model. This version has the ffxsr bit actually disabled, to match what was documented below. Thanks to Andre Przywara for spotting the bug. I am trying to be conservative with the new model, so I am enabling only features known to be useful to guests, and not enabling anything that was not tested or found to be useful to a guest. List of missing flags in comparison to real hardware: - vme: host-specific feature. - osxsave: it is not set here because it is set by the guest OS, not by KVM - monitor: this is filtered out by the KVM module, so no point in enabling it. - mmxext: untested, so not enabled. - Perf*, Topology*, lwp, ibs: not emulated by KVM. - wdt, skinit, osvw, altmovcr8, extapicspace, cmplegacy: untested, so not enabled. List of new flags, in comparison to the Opteron_G3 model: - xsave: xsave feature, already implemented by Qemu - avx, aes, sse4.x, ssse3, pclmulqdq: all new state the new instructions could use is handled by the xsave state loading/saving code on Qemu. - pdpe1gb: 1GB pages, supported by the KVM kernel module. - ffxsr: untested, so not enabled - fma4, xop: all new state the new instructions could use is handled by the xsave loading/saving code on Qemu. - 3dnowprefetch: safe to pass through, though the flag is not used by Linux guests, at least. Below is the comparison between the current Opteron_G3 model and the new model being added. - The "full" line contains the flags found on actual hardware. - The "missing" line shows the flags that are present on actual hardware, but not on the added Opteron_G4 model. - The "new" line shows the flags that were not on the Opteron_G3 model but are on Opteron_G4. feature_edx: Opteron_G3: sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu full: sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de vme fpu Opteron_G4: sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu missing: vme feature_ecx: Opteron_G3: popcnt cx16 monitor sse3 full: avx osxsave xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 monitor pclmulqdq sse3 Opteron_G4: avx xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3 missing: osxsave monitor new: avx xsave aes sse4.2 sse4.1 ssse3 pclmulqdq extfeature_edx: Opteron_G3: lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu full: lm rdtscp pdpe1gb ffxsr fxsr mmx mmxext nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de vme fpu Opteron_G4: lm rdtscp pdpe1gb fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu missing: mmxext vme new: pdpe1gb extfeature_ecx: Opteron_G3: misalignsse sse4a abm svm lahf_lm full: Perf* Topology* fma4 lwp wdt skinit xop ibs osvw 3dnowprefetch misalignsse sse4a abm altmovcr8 extapicspace svm cmplegacy lahf_lm Opteron_G4: fma4 xop 3dnowprefetch misalignsse sse4a abm svm lahf_lm new: fma4 xop 3dnowprefetch missing: Perf* Topology* lwp wdt skinit ibs osvw altmovcr8 extapicspace cmplegacy Changes v1 -> v2: - Actually disable ffxsr bit Cc: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>		2012-03-12 14:05:25 -05:00
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target	add Opteron_G4 CPU model (v2)	2012-03-12 14:05:25 -05:00