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0f9668e0c1
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
535 lines
12 KiB
C
535 lines
12 KiB
C
/*
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* RISC-V implementation of KVM hooks
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*
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* Copyright (c) 2020 Huawei Technologies Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include <sys/ioctl.h>
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#include <linux/kvm.h>
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#include "qemu/timer.h"
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#include "qemu/error-report.h"
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#include "qemu/main-loop.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "sysemu/kvm_int.h"
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#include "cpu.h"
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#include "trace.h"
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#include "hw/pci/pci.h"
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#include "exec/memattrs.h"
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#include "exec/address-spaces.h"
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#include "hw/boards.h"
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#include "hw/irq.h"
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#include "qemu/log.h"
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#include "hw/loader.h"
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#include "kvm_riscv.h"
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#include "sbi_ecall_interface.h"
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#include "chardev/char-fe.h"
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#include "migration/migration.h"
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#include "sysemu/runstate.h"
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static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
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uint64_t idx)
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{
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uint64_t id = KVM_REG_RISCV | type | idx;
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switch (riscv_cpu_mxl(env)) {
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case MXL_RV32:
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id |= KVM_REG_SIZE_U32;
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break;
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case MXL_RV64:
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id |= KVM_REG_SIZE_U64;
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break;
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default:
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g_assert_not_reached();
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}
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return id;
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}
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#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
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KVM_REG_RISCV_CORE_REG(name))
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#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
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KVM_REG_RISCV_CSR_REG(name))
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#define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
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KVM_REG_RISCV_TIMER_REG(name))
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#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
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#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
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#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
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do { \
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int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
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if (ret) { \
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return ret; \
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} \
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} while (0)
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#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
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do { \
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int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
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if (ret) { \
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return ret; \
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} \
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} while (0)
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#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \
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do { \
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int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \
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if (ret) { \
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abort(); \
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} \
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} while (0)
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#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
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do { \
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int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®); \
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if (ret) { \
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abort(); \
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} \
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} while (0)
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static int kvm_riscv_get_regs_core(CPUState *cs)
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{
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int ret = 0;
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int i;
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target_ulong reg;
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CPURISCVState *env = &RISCV_CPU(cs)->env;
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ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®);
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if (ret) {
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return ret;
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}
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env->pc = reg;
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for (i = 1; i < 32; i++) {
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uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
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ret = kvm_get_one_reg(cs, id, ®);
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if (ret) {
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return ret;
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}
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env->gpr[i] = reg;
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}
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return ret;
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}
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static int kvm_riscv_put_regs_core(CPUState *cs)
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{
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int ret = 0;
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int i;
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target_ulong reg;
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CPURISCVState *env = &RISCV_CPU(cs)->env;
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reg = env->pc;
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ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®);
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if (ret) {
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return ret;
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}
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for (i = 1; i < 32; i++) {
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uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
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reg = env->gpr[i];
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ret = kvm_set_one_reg(cs, id, ®);
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if (ret) {
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return ret;
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}
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}
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return ret;
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}
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static int kvm_riscv_get_regs_csr(CPUState *cs)
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{
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int ret = 0;
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CPURISCVState *env = &RISCV_CPU(cs)->env;
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KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
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KVM_RISCV_GET_CSR(cs, env, sie, env->mie);
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KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec);
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KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch);
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KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc);
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KVM_RISCV_GET_CSR(cs, env, scause, env->scause);
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KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
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KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
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KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
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return ret;
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}
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static int kvm_riscv_put_regs_csr(CPUState *cs)
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{
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int ret = 0;
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CPURISCVState *env = &RISCV_CPU(cs)->env;
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KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
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KVM_RISCV_SET_CSR(cs, env, sie, env->mie);
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KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec);
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KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch);
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KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc);
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KVM_RISCV_SET_CSR(cs, env, scause, env->scause);
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KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
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KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
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KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
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return ret;
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}
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static int kvm_riscv_get_regs_fp(CPUState *cs)
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{
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int ret = 0;
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int i;
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CPURISCVState *env = &RISCV_CPU(cs)->env;
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if (riscv_has_ext(env, RVD)) {
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uint64_t reg;
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for (i = 0; i < 32; i++) {
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ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
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if (ret) {
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return ret;
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}
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env->fpr[i] = reg;
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}
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return ret;
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}
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if (riscv_has_ext(env, RVF)) {
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uint32_t reg;
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for (i = 0; i < 32; i++) {
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ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
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if (ret) {
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return ret;
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}
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env->fpr[i] = reg;
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}
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return ret;
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}
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return ret;
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}
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static int kvm_riscv_put_regs_fp(CPUState *cs)
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{
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int ret = 0;
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int i;
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CPURISCVState *env = &RISCV_CPU(cs)->env;
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if (riscv_has_ext(env, RVD)) {
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uint64_t reg;
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for (i = 0; i < 32; i++) {
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reg = env->fpr[i];
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ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
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if (ret) {
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return ret;
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}
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}
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return ret;
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}
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if (riscv_has_ext(env, RVF)) {
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uint32_t reg;
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for (i = 0; i < 32; i++) {
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reg = env->fpr[i];
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ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
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if (ret) {
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return ret;
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}
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}
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return ret;
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}
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return ret;
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}
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static void kvm_riscv_get_regs_timer(CPUState *cs)
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{
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CPURISCVState *env = &RISCV_CPU(cs)->env;
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if (env->kvm_timer_dirty) {
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return;
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}
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KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time);
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KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare);
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KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state);
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KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency);
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env->kvm_timer_dirty = true;
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}
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static void kvm_riscv_put_regs_timer(CPUState *cs)
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{
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uint64_t reg;
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CPURISCVState *env = &RISCV_CPU(cs)->env;
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if (!env->kvm_timer_dirty) {
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return;
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}
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KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time);
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KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare);
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/*
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* To set register of RISCV_TIMER_REG(state) will occur a error from KVM
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* on env->kvm_timer_state == 0, It's better to adapt in KVM, but it
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* doesn't matter that adaping in QEMU now.
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* TODO If KVM changes, adapt here.
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*/
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if (env->kvm_timer_state) {
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KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state);
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}
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/*
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* For now, migration will not work between Hosts with different timer
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* frequency. Therefore, we should check whether they are the same here
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* during the migration.
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*/
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if (migration_is_running(migrate_get_current()->state)) {
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KVM_RISCV_GET_TIMER(cs, env, frequency, reg);
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if (reg != env->kvm_timer_frequency) {
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error_report("Dst Hosts timer frequency != Src Hosts");
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}
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}
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env->kvm_timer_dirty = false;
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}
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const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
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KVM_CAP_LAST_INFO
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};
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int kvm_arch_get_registers(CPUState *cs)
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{
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int ret = 0;
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ret = kvm_riscv_get_regs_core(cs);
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if (ret) {
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return ret;
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}
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ret = kvm_riscv_get_regs_csr(cs);
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if (ret) {
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return ret;
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}
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ret = kvm_riscv_get_regs_fp(cs);
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if (ret) {
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return ret;
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}
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return ret;
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}
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int kvm_arch_put_registers(CPUState *cs, int level)
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{
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int ret = 0;
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ret = kvm_riscv_put_regs_core(cs);
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if (ret) {
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return ret;
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}
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ret = kvm_riscv_put_regs_csr(cs);
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if (ret) {
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return ret;
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}
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ret = kvm_riscv_put_regs_fp(cs);
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if (ret) {
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return ret;
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}
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return ret;
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}
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int kvm_arch_release_virq_post(int virq)
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{
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return 0;
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}
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int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
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uint64_t address, uint32_t data, PCIDevice *dev)
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{
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return 0;
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}
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int kvm_arch_destroy_vcpu(CPUState *cs)
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{
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return 0;
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}
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unsigned long kvm_arch_vcpu_id(CPUState *cpu)
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{
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return cpu->cpu_index;
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}
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static void kvm_riscv_vm_state_change(void *opaque, bool running,
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RunState state)
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{
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CPUState *cs = opaque;
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if (running) {
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kvm_riscv_put_regs_timer(cs);
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} else {
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kvm_riscv_get_regs_timer(cs);
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}
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}
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void kvm_arch_init_irq_routing(KVMState *s)
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{
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}
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int kvm_arch_init_vcpu(CPUState *cs)
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{
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int ret = 0;
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target_ulong isa;
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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uint64_t id;
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qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs);
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id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
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KVM_REG_RISCV_CONFIG_REG(isa));
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ret = kvm_get_one_reg(cs, id, &isa);
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if (ret) {
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return ret;
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}
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env->misa_ext = isa;
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return ret;
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}
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int kvm_arch_msi_data_to_gsi(uint32_t data)
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{
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abort();
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}
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int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
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int vector, PCIDevice *dev)
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{
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return 0;
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}
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int kvm_arch_init(MachineState *ms, KVMState *s)
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{
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return 0;
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}
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int kvm_arch_irqchip_create(KVMState *s)
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{
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return 0;
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}
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int kvm_arch_process_async_events(CPUState *cs)
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{
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return 0;
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}
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void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
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{
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}
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MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
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{
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return MEMTXATTRS_UNSPECIFIED;
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}
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bool kvm_arch_stop_on_emulation_error(CPUState *cs)
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{
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return true;
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}
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static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
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{
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int ret = 0;
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unsigned char ch;
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switch (run->riscv_sbi.extension_id) {
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case SBI_EXT_0_1_CONSOLE_PUTCHAR:
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ch = run->riscv_sbi.args[0];
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qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
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break;
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case SBI_EXT_0_1_CONSOLE_GETCHAR:
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ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
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if (ret == sizeof(ch)) {
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run->riscv_sbi.args[0] = ch;
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} else {
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run->riscv_sbi.args[0] = -1;
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}
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: un-handled SBI EXIT, specific reasons is %lu\n",
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__func__, run->riscv_sbi.extension_id);
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ret = -1;
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break;
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}
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return ret;
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}
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int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
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{
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int ret = 0;
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switch (run->exit_reason) {
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case KVM_EXIT_RISCV_SBI:
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ret = kvm_riscv_handle_sbi(cs, run);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
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__func__, run->exit_reason);
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ret = -1;
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break;
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}
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return ret;
|
|
}
|
|
|
|
void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
|
|
{
|
|
CPURISCVState *env = &cpu->env;
|
|
|
|
if (!kvm_enabled()) {
|
|
return;
|
|
}
|
|
env->pc = cpu->env.kernel_addr;
|
|
env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
|
|
env->gpr[11] = cpu->env.fdt_addr; /* a1 */
|
|
env->satp = 0;
|
|
}
|
|
|
|
void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
|
|
{
|
|
int ret;
|
|
unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
|
|
|
|
if (irq != IRQ_S_EXT) {
|
|
perror("kvm riscv set irq != IRQ_S_EXT\n");
|
|
abort();
|
|
}
|
|
|
|
ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
|
|
if (ret < 0) {
|
|
perror("Set irq failed");
|
|
abort();
|
|
}
|
|
}
|
|
|
|
bool kvm_arch_cpu_check_are_resettable(void)
|
|
{
|
|
return true;
|
|
}
|