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3cbee15b9a
* make PowerPC NVRAM accessors generic to be able to use a MacIO NVRAM instead of the M48T59 one * split PowerMac targets code: - move all PowerMac related definitions and prototypes into hw/ppc_mac.h - add hw/mac_dbdma.c, hw/mac_nvram.c and macio.c which implements shared PowerMac devices - define the g3bw machine in a new hw/ppc_oldworld.c file * Fix the g3bw target: - fix the Grackle host PCI device - connect the Heathrow PIC to the PowerPC 6xx bus pins git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3475 c046a42c-6fe2-441c-8c8c-71466251a162
124 lines
3.4 KiB
C
124 lines
3.4 KiB
C
/*
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* PowerMac NVRAM emulation
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*
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* Copyright (c) 2005-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#include "ppc_mac.h"
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struct MacIONVRAMState {
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uint8_t data[0x2000];
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};
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/* Direct access to NVRAM */
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uint32_t macio_nvram_read (void *opaque, uint32_t addr)
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{
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MacIONVRAMState *s = opaque;
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uint32_t ret;
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// printf("%s: %p addr %04x\n", __func__, s, addr);
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if (addr < 0x2000)
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ret = s->data[addr];
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else
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ret = -1;
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return ret;
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}
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void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
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{
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MacIONVRAMState *s = opaque;
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// printf("%s: %p addr %04x val %02x\n", __func__, s, addr, val);
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if (addr < 0x2000)
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s->data[addr] = val;
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}
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/* macio style NVRAM device */
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static void macio_nvram_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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MacIONVRAMState *s = opaque;
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addr = (addr >> 4) & 0x1fff;
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s->data[addr] = value;
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// printf("macio_nvram_writeb %04x = %02x\n", addr, value);
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}
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static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
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{
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MacIONVRAMState *s = opaque;
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uint32_t value;
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addr = (addr >> 4) & 0x1fff;
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value = s->data[addr];
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// printf("macio_nvram_readb %04x = %02x\n", addr, value);
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return value;
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}
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static CPUWriteMemoryFunc *nvram_write[] = {
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&macio_nvram_writeb,
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&macio_nvram_writeb,
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&macio_nvram_writeb,
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};
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static CPUReadMemoryFunc *nvram_read[] = {
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&macio_nvram_readb,
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&macio_nvram_readb,
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&macio_nvram_readb,
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};
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MacIONVRAMState *macio_nvram_init (int *mem_index)
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{
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MacIONVRAMState *s;
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s = qemu_mallocz(sizeof(MacIONVRAMState));
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if (!s)
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return NULL;
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*mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
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return s;
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}
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static uint8_t nvram_chksum (const uint8_t *buf, int n)
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{
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int sum, i;
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sum = 0;
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for(i = 0; i < n; i++)
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sum += buf[i];
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return (sum & 0xff) + (sum >> 8);
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}
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/* set a free Mac OS NVRAM partition */
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void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len)
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{
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uint8_t *buf;
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char partition_name[12] = "wwwwwwwwwwww";
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buf = nvr->data;
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buf[0] = 0x7f; /* free partition magic */
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buf[1] = 0; /* checksum */
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buf[2] = len >> 8;
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buf[3] = len;
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memcpy(buf + 4, partition_name, 12);
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buf[1] = nvram_chksum(buf, 16);
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}
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