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xemu/target-tilegx
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Chen Gang 2a080ce266 target-tilegx: Implement prefetch instructions in pipe y2 
Originally, tilegx qemu only implement prefetch instructions in pipe x1,
did not implement them in pipe y2.

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-22 07:51:49 -10:00
..
cpu.c qdev: Protect device-list-properties against broken devices 2015-10-09 15:25:57 +02:00
cpu.h Do away with TB retranslation 2015-10-08 15:33:56 +01:00
helper.c target-tilegx: Support iret instruction and related special registers 2015-10-07 20:24:04 +11:00
helper.h target-tilegx: Support iret instruction and related special registers 2015-10-07 20:24:04 +11:00
Makefile.objs target-tilegx: Handle v1shl, v1shru, v1shrs 2015-09-15 07:45:34 -07:00
opcode_tilegx.h target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 2015-09-15 07:41:35 -07:00
simd_helper.c target-tilegx: Implement v2mults instruction 2015-10-07 20:03:16 +11:00
spr_def_64.h target-tilegx: Add special register information from Tilera Corporation 2015-09-15 07:41:35 -07:00
translate.c target-tilegx: Implement prefetch instructions in pipe y2 2015-10-22 07:51:49 -10:00