Bin Meng 138ca49a82 target/riscv: Remove built-in GDB XML files for CSRs ... Now that we have switched to generate the RISC-V CSR XML dynamically, remove the built-in hardcoded XML files. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210116054123.5457-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-01-16 10:57:21 -08:00
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aarch64-core.xml
aarch64-fpu.xml
arm-core.xml
arm-m-profile.xml	target/arm: Use correct GDB XML for M-profile cores	2020-05-14 15:03:08 +01:00
arm-neon.xml
arm-vfp3.xml
arm-vfp.xml
avr-cpu.xml	target/avr: CPU class: Add GDB support	2020-07-10 17:58:32 +02:00
cf-core.xml
cf-fp.xml
i386-32bit.xml	gdbstub: Fix i386/x86_64 machine description and add control registers	2019-02-05 16:50:18 +01:00
i386-64bit.xml	gdbstub: Fix i386/x86_64 machine description and add control registers	2019-02-05 16:50:18 +01:00
m68k-core.xml	target/m68k: fix gdb for m68xxx	2020-05-06 09:29:26 +01:00
m68k-fp.xml	target-m68k: define 96bit FP registers for gdb on 680x0	2017-06-21 22:11:12 +02:00
power64-core.xml
power-altivec.xml
power-core.xml
power-fpu.xml
power-spe.xml
power-vsx.xml
riscv-32bit-cpu.xml	RISC-V: Add 32-bit gdb xml files.	2019-03-19 05:13:24 -07:00
riscv-32bit-fpu.xml	RISC-V: Add 64-bit gdb xml files.	2019-03-19 05:13:24 -07:00
riscv-32bit-virtual.xml	target/riscv: Expose "priv" register for GDB for reads	2019-10-28 07:47:29 -07:00
riscv-64bit-cpu.xml	RISC-V: Add 64-bit gdb xml files.	2019-03-19 05:13:24 -07:00
riscv-64bit-fpu.xml	RISC-V: Add 64-bit gdb xml files.	2019-03-19 05:13:24 -07:00
riscv-64bit-virtual.xml	target/riscv: Expose "priv" register for GDB for reads	2019-10-28 07:47:29 -07:00
rx-core.xml	target/rx: CPU definitions	2020-03-19 17:58:05 +01:00
s390-acr.xml
s390-cr.xml
s390-fpr.xml
s390-gs.xml	s390x/gdb: add gs registers	2017-07-14 12:29:49 +02:00
s390-virt.xml
s390-vx.xml
s390x-core64.xml