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Since HAX_VM_IOCTL_ALLOC_RAM takes a 32-bit size, it cannot handle RAM blocks of 4GB or larger, which is why HAXM can only run guests with less than 4GB of RAM. Solve this problem by utilizing the new HAXM API, HAX_VM_IOCTL_ADD_RAMBLOCK, which takes a 64-bit size, to register RAM blocks with the HAXM kernel module. The new API is first added in HAXM 7.0.0, and its availablility and be confirmed by the presence of the HAX_CAP_64BIT_RAMBLOCK capability flag. When the guest RAM size reaches 7GB, QEMU will ask HAXM to set up a memory mapping that covers a 4GB region, which will fail, because HAX_VM_IOCTL_SET_RAM also takes a 32-bit size. Work around this limitation by splitting the large mapping into small ones and calling HAX_VM_IOCTL_SET_RAM multiple times. Bug: https://bugs.launchpad.net/qemu/+bug/1735576 Signed-off-by: Yu Ning <yu.ning@intel.com> Message-Id: <1515752555-12784-1-git-send-email-yu.ning@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
370 lines
8.6 KiB
C
370 lines
8.6 KiB
C
/*
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* QEMU HAXM support
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*
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* Copyright (c) 2011 Intel Corporation
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* Written by:
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* Jiang Yunhong<yunhong.jiang@intel.com>
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* Xin Xiaohui<xiaohui.xin@intel.com>
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* Zhang Xiantao<xiantao.zhang@intel.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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/* Interface with HAX kernel module */
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#ifndef _HAX_INTERFACE_H
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#define _HAX_INTERFACE_H
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/* fx_layout has 3 formats table 3-56, 512bytes */
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struct fx_layout {
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uint16_t fcw;
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uint16_t fsw;
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uint8_t ftw;
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uint8_t res1;
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uint16_t fop;
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union {
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struct {
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uint32_t fip;
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uint16_t fcs;
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uint16_t res2;
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};
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uint64_t fpu_ip;
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};
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union {
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struct {
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uint32_t fdp;
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uint16_t fds;
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uint16_t res3;
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};
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uint64_t fpu_dp;
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};
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uint32_t mxcsr;
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uint32_t mxcsr_mask;
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uint8_t st_mm[8][16];
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uint8_t mmx_1[8][16];
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uint8_t mmx_2[8][16];
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uint8_t pad[96];
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} __attribute__ ((aligned(8)));
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struct vmx_msr {
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uint64_t entry;
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uint64_t value;
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} __attribute__ ((__packed__));
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/*
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* Fixed array is not good, but it makes Mac support a bit easier by avoiding
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* memory map or copyin staff.
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*/
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#define HAX_MAX_MSR_ARRAY 0x20
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struct hax_msr_data {
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uint16_t nr_msr;
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uint16_t done;
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uint16_t pad[2];
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struct vmx_msr entries[HAX_MAX_MSR_ARRAY];
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} __attribute__ ((__packed__));
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union interruptibility_state_t {
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uint32_t raw;
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struct {
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uint32_t sti_blocking:1;
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uint32_t movss_blocking:1;
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uint32_t smi_blocking:1;
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uint32_t nmi_blocking:1;
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uint32_t reserved:28;
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};
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uint64_t pad;
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};
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typedef union interruptibility_state_t interruptibility_state_t;
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/* Segment descriptor */
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struct segment_desc_t {
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uint16_t selector;
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uint16_t _dummy;
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uint32_t limit;
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uint64_t base;
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union {
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struct {
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uint32_t type:4;
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uint32_t desc:1;
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uint32_t dpl:2;
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uint32_t present:1;
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uint32_t:4;
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uint32_t available:1;
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uint32_t long_mode:1;
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uint32_t operand_size:1;
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uint32_t granularity:1;
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uint32_t null:1;
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uint32_t:15;
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};
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uint32_t ar;
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};
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uint32_t ipad;
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};
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typedef struct segment_desc_t segment_desc_t;
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struct vcpu_state_t {
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union {
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uint64_t _regs[16];
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struct {
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union {
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struct {
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uint8_t _al, _ah;
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};
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uint16_t _ax;
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uint32_t _eax;
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uint64_t _rax;
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};
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union {
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struct {
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uint8_t _cl, _ch;
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};
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uint16_t _cx;
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uint32_t _ecx;
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uint64_t _rcx;
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};
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union {
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struct {
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uint8_t _dl, _dh;
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};
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uint16_t _dx;
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uint32_t _edx;
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uint64_t _rdx;
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};
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union {
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struct {
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uint8_t _bl, _bh;
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};
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uint16_t _bx;
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uint32_t _ebx;
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uint64_t _rbx;
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};
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union {
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uint16_t _sp;
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uint32_t _esp;
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uint64_t _rsp;
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};
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union {
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uint16_t _bp;
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uint32_t _ebp;
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uint64_t _rbp;
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};
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union {
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uint16_t _si;
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uint32_t _esi;
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uint64_t _rsi;
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};
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union {
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uint16_t _di;
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uint32_t _edi;
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uint64_t _rdi;
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};
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uint64_t _r8;
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uint64_t _r9;
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uint64_t _r10;
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uint64_t _r11;
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uint64_t _r12;
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uint64_t _r13;
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uint64_t _r14;
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uint64_t _r15;
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};
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};
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union {
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uint32_t _eip;
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uint64_t _rip;
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};
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union {
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uint32_t _eflags;
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uint64_t _rflags;
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};
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segment_desc_t _cs;
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segment_desc_t _ss;
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segment_desc_t _ds;
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segment_desc_t _es;
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segment_desc_t _fs;
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segment_desc_t _gs;
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segment_desc_t _ldt;
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segment_desc_t _tr;
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segment_desc_t _gdt;
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segment_desc_t _idt;
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uint64_t _cr0;
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uint64_t _cr2;
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uint64_t _cr3;
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uint64_t _cr4;
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uint64_t _dr0;
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uint64_t _dr1;
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uint64_t _dr2;
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uint64_t _dr3;
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uint64_t _dr6;
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uint64_t _dr7;
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uint64_t _pde;
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uint32_t _efer;
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uint32_t _sysenter_cs;
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uint64_t _sysenter_eip;
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uint64_t _sysenter_esp;
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uint32_t _activity_state;
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uint32_t pad;
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interruptibility_state_t _interruptibility_state;
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};
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/* HAX exit status */
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enum exit_status {
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/* IO port request */
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HAX_EXIT_IO = 1,
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/* MMIO instruction emulation */
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HAX_EXIT_MMIO,
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/* QEMU emulation mode request, currently means guest enter non-PG mode */
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HAX_EXIT_REAL,
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/*
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* Interrupt window open, qemu can inject interrupt now
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* Also used when signal pending since at that time qemu usually need
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* check interrupt
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*/
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HAX_EXIT_INTERRUPT,
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/* Unknown vmexit, mostly trigger reboot */
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HAX_EXIT_UNKNOWN_VMEXIT,
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/* HALT from guest */
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HAX_EXIT_HLT,
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/* Reboot request, like because of tripple fault in guest */
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HAX_EXIT_STATECHANGE,
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/* the vcpu is now only paused when destroy, so simply return to hax */
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HAX_EXIT_PAUSED,
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HAX_EXIT_FAST_MMIO,
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};
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/*
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* The interface definition:
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* 1. vcpu_run execute will return 0 on success, otherwise mean failed
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* 2. exit_status return the exit reason, as stated in enum exit_status
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* 3. exit_reason is the vmx exit reason
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*/
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struct hax_tunnel {
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uint32_t _exit_reason;
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uint32_t _exit_flag;
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uint32_t _exit_status;
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uint32_t user_event_pending;
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int ready_for_interrupt_injection;
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int request_interrupt_window;
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union {
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struct {
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/* 0: read, 1: write */
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#define HAX_EXIT_IO_IN 1
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#define HAX_EXIT_IO_OUT 0
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uint8_t _direction;
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uint8_t _df;
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uint16_t _size;
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uint16_t _port;
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uint16_t _count;
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uint8_t _flags;
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uint8_t _pad0;
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uint16_t _pad1;
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uint32_t _pad2;
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uint64_t _vaddr;
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} pio;
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struct {
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uint64_t gla;
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} mmio;
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struct {
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} state;
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};
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} __attribute__ ((__packed__));
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struct hax_module_version {
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uint32_t compat_version;
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uint32_t cur_version;
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} __attribute__ ((__packed__));
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/* This interface is support only after API version 2 */
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struct hax_qemu_version {
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/* Current API version in QEMU */
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uint32_t cur_version;
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/* The minimum API version supported by QEMU */
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uint32_t min_version;
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} __attribute__ ((__packed__));
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/* The mac specfic interface to qemu, mostly is ioctl related */
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struct hax_tunnel_info {
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uint64_t va;
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uint64_t io_va;
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uint16_t size;
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uint16_t pad[3];
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} __attribute__ ((__packed__));
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struct hax_alloc_ram_info {
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uint32_t size;
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uint32_t pad;
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uint64_t va;
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} __attribute__ ((__packed__));
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struct hax_ramblock_info {
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uint64_t start_va;
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uint64_t size;
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uint64_t reserved;
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} __attribute__ ((__packed__));
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#define HAX_RAM_INFO_ROM 0x01 /* Read-Only */
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#define HAX_RAM_INFO_INVALID 0x80 /* Unmapped, usually used for MMIO */
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struct hax_set_ram_info {
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uint64_t pa_start;
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uint32_t size;
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uint8_t flags;
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uint8_t pad[3];
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uint64_t va;
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} __attribute__ ((__packed__));
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#define HAX_CAP_STATUS_WORKING 0x1
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#define HAX_CAP_STATUS_NOTWORKING 0x0
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#define HAX_CAP_WORKSTATUS_MASK 0x1
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#define HAX_CAP_FAILREASON_VT 0x1
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#define HAX_CAP_FAILREASON_NX 0x2
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#define HAX_CAP_MEMQUOTA 0x2
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#define HAX_CAP_UG 0x4
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#define HAX_CAP_64BIT_RAMBLOCK 0x8
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struct hax_capabilityinfo {
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/* bit 0: 1 - working
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* 0 - not working, possibly because NT/NX disabled
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* bit 1: 1 - memory limitation working
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* 0 - no memory limitation
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*/
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uint16_t wstatus;
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/* valid when not working
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* bit 0: VT not enabeld
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* bit 1: NX not enabled*/
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uint16_t winfo;
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uint32_t pad;
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uint64_t mem_quota;
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} __attribute__ ((__packed__));
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struct hax_fastmmio {
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uint64_t gpa;
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union {
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uint64_t value;
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uint64_t gpa2; /* since HAX API v4 */
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};
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uint8_t size;
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uint8_t direction;
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uint16_t reg_index;
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uint32_t pad0;
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uint64_t _cr0;
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uint64_t _cr2;
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uint64_t _cr3;
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uint64_t _cr4;
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} __attribute__ ((__packed__));
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#endif
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