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https://github.com/xemu-project/xemu.git
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00914b7d97
Add the first Microblaze little endian platform. Platform uses uart16550, axi ethernet, timer, intc. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
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/* OPB Interrupt Controller. */
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qemu_irq *microblaze_pic_init_cpu(CPUState *env);
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static inline DeviceState *
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xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr)
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{
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DeviceState *dev;
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dev = qdev_create(NULL, "xilinx,intc");
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qdev_prop_set_uint32(dev, "kind-of-intr", kind_of_intr);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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/* OPB Timer/Counter. */
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static inline DeviceState *
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xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int nr, int freq)
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{
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DeviceState *dev;
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dev = qdev_create(NULL, "xilinx,timer");
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qdev_prop_set_uint32(dev, "nr-timers", nr);
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qdev_prop_set_uint32(dev, "frequency", freq);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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/* XPS Ethernet Lite MAC. */
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static inline DeviceState *
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xilinx_ethlite_create(NICInfo *nd, target_phys_addr_t base, qemu_irq irq,
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int txpingpong, int rxpingpong)
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{
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DeviceState *dev;
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qemu_check_nic_model(nd, "xilinx-ethlite");
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dev = qdev_create(NULL, "xilinx,ethlite");
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qdev_set_nic_properties(dev, nd);
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qdev_prop_set_uint32(dev, "txpingpong", txpingpong);
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qdev_prop_set_uint32(dev, "rxpingpong", rxpingpong);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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static inline DeviceState *
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xilinx_axiethernet_create(void *dmach,
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NICInfo *nd, target_phys_addr_t base, qemu_irq irq,
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int txmem, int rxmem)
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{
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DeviceState *dev;
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qemu_check_nic_model(nd, "xilinx-axienet");
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dev = qdev_create(NULL, "xilinx,axienet");
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qdev_set_nic_properties(dev, nd);
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qdev_prop_set_uint32(dev, "c_rxmem", rxmem);
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qdev_prop_set_uint32(dev, "c_txmem", txmem);
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qdev_prop_set_ptr(dev, "dmach", dmach);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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static inline DeviceState *
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xilinx_axiethernetdma_create(void *dmach,
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target_phys_addr_t base, qemu_irq irq,
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qemu_irq irq2, int freqhz)
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{
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DeviceState *dev = NULL;
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dev = qdev_create(NULL, "xilinx,axidma");
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qdev_prop_set_uint32(dev, "freqhz", freqhz);
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qdev_prop_set_ptr(dev, "dmach", dmach);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq2);
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sysbus_connect_irq(sysbus_from_qdev(dev), 1, irq);
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return dev;
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}
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