James Hogan d673a68db6 target/mips: Fix RDHWR CC with icount ...

RDHWR CC reads the CPU timer like MFC0 CP0_Count, so with icount enabled
it must set can_do_io while it calls the helper to avoid the "Bad icount
read" error. It should also break out of the translation loop to ensure
that timer interrupts are immediately handled.

Fixes: 2e70f6efa8b9 ("Add instruction counter.")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>

2017-08-02 22:18:13 +01:00

..

cpu-qom.h

…

cpu.c

qom/cpu: move tlb_flush to cpu_common_reset

2017-01-13 14:24:31 +00:00

cpu.h

target/mips: Add segmentation control registers

2017-07-20 22:42:26 +01:00

dsp_helper.c

…

gdbstub.c

…

helper.c

mips: Add KVM T&E segment support for TCG

2017-08-02 22:18:06 +01:00

helper.h

target/mips: Add segmentation control registers

2017-07-20 22:42:26 +01:00

kvm_mips.h

…

kvm.c

vcpu_dirty: share the same field in CPUState for all accelerators

2017-07-04 14:30:03 +02:00

lmi_helper.c

…

machine.c

target/mips: Add segmentation control registers

2017-07-20 22:42:26 +01:00

Makefile.objs

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mips-defs.h

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mips-semi.c

…

msa_helper.c

…

op_helper.c

target-mips: apply CP0.PageMask before writing into TLB entry

2017-08-02 22:18:11 +01:00

TODO

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trace-events

docs: fix broken paths to docs/devel/tracing.txt

2017-07-31 13:12:53 +03:00

translate_init.c

target/mips: Enable CP0_EBase.WG on MIPS64 CPUs

2017-07-21 03:23:44 +01:00

translate.c

target/mips: Fix RDHWR CC with icount

2017-08-02 22:18:13 +01:00