Richard Henderson 9960237769 target/arm: Honor the HCR_EL2.TACR bit ... This bit traps EL1 access to the auxiliary control registers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2020-03-05 16:09:18 +00:00
..
alpha
arm	target/arm: Honor the HCR_EL2.TACR bit	2020-03-05 16:09:18 +00:00
cris
hppa
i386	Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEAD	2020-02-25 13:41:48 +01:00
lm32
m68k
microblaze
mips
moxie
nios2
openrisc
ppc	target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition	2020-02-21 09:15:04 +11:00
riscv	target/riscv: Emulate TIME CSRs for privileged mode	2020-02-27 13:46:36 -08:00
s390x	s390x: Rename and use constants for short PSW address and mask	2020-02-27 11:10:29 +01:00
sh4
sparc
tilegx
tricore
unicore32
xtensa