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xemu/hw/mips
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Philippe Mathieu-Daudé 9a2133f45c hw/mips/malta: Fix FPGA I/O region size 
The FPGA present on the CoreCard has an I/O region 1MiB wide.

Refs:
- Atlas User’s Manual (Document Number: MD00005)
- Malta User’s Manual (Document Number: MD00048)

Fixes: ea85df72b60 ("mips_malta: convert to memory API")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200905213049.761949-1-f4bug@amsat.org>
2020-10-17 13:59:40 +02:00
..
addr.c
…
boston.c
hw/mips/boston: Set CPU frequency to 1 GHz
2020-10-17 13:59:40 +02:00
cps.c
hw/mips/cps: Do not allow use without input clock
2020-10-17 13:59:40 +02:00
fuloong2e.c
hw/mips/fuloong2e: Set CPU frequency to 533 MHz
2020-10-17 13:59:40 +02:00
gt64xxx_pci.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
jazz.c
hw/mips/jazz: Correct CPU frequencies
2020-10-17 13:59:40 +02:00
Kconfig
…
malta.c
hw/mips/malta: Fix FPGA I/O region size
2020-10-17 13:59:40 +02:00
meson.build
configure: do not include dependency flags in QEMU_CFLAGS and LIBS
2020-09-08 11:43:16 +02:00
mips_int.c
…
mipssim.c
hw/mips/mipssim: Correct CPU frequency
2020-10-17 13:59:40 +02:00
r4k.c
hw/mips/r4k: Explicit CPU frequency is 200 MHz
2020-10-17 13:59:40 +02:00
trace-events
trace-events: Fix attribution of trace points to source
2020-09-09 17:17:58 +01:00
trace.h
…