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Richard Henderson 9b253fe554 target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state 
By performing this store early, we avoid having to save and restore
the register holding the address around any function calls.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191023150057.25731-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24 17:16:28 +01:00
..
alpha
target/alpha: Tidy helper_fp_exc_raise_s
2019-09-26 19:00:53 +01:00
arm
target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state
2019-10-24 17:16:28 +01:00
cris
Monitor patches for 2019-08-21
2019-08-22 10:31:21 +01:00
hppa
target/hppa: prevent trashing of temporary in do_depw_sar()
2019-09-14 15:39:24 -04:00
i386
target/i386: Introduce Denverton CPU model
2019-10-23 23:37:42 -03:00
lm32
Monitor patches for 2019-08-21
2019-08-22 10:31:21 +01:00
m68k
target/m68k/fpu_helper.c: rename the access arguments
2019-09-19 12:12:19 +02:00
microblaze
tcg: TCGMemOp is now accelerator independent MemOp
2019-09-03 08:30:38 -07:00
mips
target/mips: msa: Move helpers for <AND|NOR|OR|XOR>.V
2019-10-01 16:58:45 +02:00
moxie
hw/core: Move cpu.c, cpu.h from qom/ to hw/core/
2019-08-21 13:24:01 +02:00
nios2
Monitor patches for 2019-08-21
2019-08-22 10:31:21 +01:00
openrisc
target/openrisc: Update cpu "any" to v1.3
2019-09-04 13:01:56 -07:00
ppc
target/ppc: Fix for optimized vsl/vsr instructions
2019-10-24 09:36:55 +11:00
riscv
gdbstub: riscv: fix the fflags registers
2019-09-17 08:42:50 -07:00
s390x
s390x/kvm: Set default cpu model for all machine classes
2019-10-21 18:03:08 +02:00
sh4
Monitor patches for 2019-08-21
2019-08-22 10:31:21 +01:00
sparc
target/sparc: Switch to do_transaction_failed() hook
2019-09-17 12:01:00 +01:00
tilegx
tcg: TCGMemOp is now accelerator independent MemOp
2019-09-03 08:30:38 -07:00
tricore
tcg: TCGMemOp is now accelerator independent MemOp
2019-09-03 08:30:38 -07:00
unicore32
Monitor patches for 2019-08-21
2019-08-22 10:31:21 +01:00
xtensa
target/xtensa: regenerate and re-import test_mmuhifi_c3 core
2019-10-18 19:54:27 -07:00