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The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-20-peter.maydell@linaro.org
135 lines
3.5 KiB
C
135 lines
3.5 KiB
C
/*
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* ARM SSE-200 CPU_IDENTITY register block
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*
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* Copyright (c) 2019 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "CPU_IDENTITY" register block which is part of the
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* Arm SSE-200 and documented in
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* http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
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*
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* It consists of one read-only CPUID register (set by QOM property), plus the
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* usual ID registers.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "sysemu/sysemu.h"
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/misc/armsse-cpuid.h"
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REG32(CPUID, 0x0)
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REG32(PID4, 0xfd0)
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REG32(PID5, 0xfd4)
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REG32(PID6, 0xfd8)
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REG32(PID7, 0xfdc)
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REG32(PID0, 0xfe0)
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REG32(PID1, 0xfe4)
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REG32(PID2, 0xfe8)
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REG32(PID3, 0xfec)
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REG32(CID0, 0xff0)
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REG32(CID1, 0xff4)
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REG32(CID2, 0xff8)
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REG32(CID3, 0xffc)
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/* PID/CID values */
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static const int sysinfo_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0x58, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static uint64_t armsse_cpuid_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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ARMSSECPUID *s = ARMSSE_CPUID(opaque);
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uint64_t r;
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switch (offset) {
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case A_CPUID:
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r = s->cpuid;
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break;
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case A_PID4 ... A_CID3:
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r = sysinfo_id[(offset - A_PID4) / 4];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE CPU_IDENTITY read: bad offset 0x%x\n", (int)offset);
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r = 0;
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break;
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}
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trace_armsse_cpuid_read(offset, r, size);
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return r;
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}
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static void armsse_cpuid_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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trace_armsse_cpuid_write(offset, value, size);
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE CPU_IDENTITY: write to RO offset 0x%x\n", (int)offset);
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}
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static const MemoryRegionOps armsse_cpuid_ops = {
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.read = armsse_cpuid_read,
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.write = armsse_cpuid_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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/* byte/halfword accesses are just zero-padded on reads and writes */
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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};
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static Property armsse_cpuid_props[] = {
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DEFINE_PROP_UINT32("CPUID", ARMSSECPUID, cpuid, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void armsse_cpuid_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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ARMSSECPUID *s = ARMSSE_CPUID(obj);
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memory_region_init_io(&s->iomem, obj, &armsse_cpuid_ops,
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s, "armsse-cpuid", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void armsse_cpuid_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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/*
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* This device has no guest-modifiable state and so it
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* does not need a reset function or VMState.
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*/
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dc->props = armsse_cpuid_props;
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}
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static const TypeInfo armsse_cpuid_info = {
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.name = TYPE_ARMSSE_CPUID,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARMSSECPUID),
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.instance_init = armsse_cpuid_init,
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.class_init = armsse_cpuid_class_init,
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};
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static void armsse_cpuid_register_types(void)
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{
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type_register_static(&armsse_cpuid_info);
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}
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type_init(armsse_cpuid_register_types);
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