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9db0855e85
* update MAINTAINERS for Alistair's new email address * add Arm v8.2 FP16 arithmetic extension for linux-user * implement display connector emulation for vexpress board * xilinx_spips: Enable only two slaves when reading/writing with stripe * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands * hw: register: Run post_write hook on reset -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJal+KGAAoJEDwlJe0UNgzeYkgP/jgaMPdRG1nSRL12SXhQi9yO O95PDRmnoGmtAzb1hOZmQATrcFmRoLnv1irCFVycGrGtfwnxXC7kuJVKI9QJ+T+0 r0jSg/TpKGchRFvIuu+JLHNttuonQln890dPJiR860TVclBjnD+PFvzEX1gI2Lhw gOnB+EL5UTMcs8Zj/HNqtAQfwQdW8yq/dDZW4/B0dQaBC0+/Qy+pRHCAp4nSbELI QLM/tIu2mz6++GlMbjN3Radkl3gdIuYWzcf9R5gZ4xlwaUwihDOOmSJ0x+41eyVy FUGfza5KEEBlRjU9ZzaJ/fIq4DMStIEugaEujr1UpKmwQB/kJoBX2iX6tP6ndgLf Pt3dxdOcJI4RyZzUZwEBUi0M4tnBZVCpOMb4zTw/IwS4ELhGiIGOeZD+j9UihTVr /Ply5G9/fC0mv4jVEQcug9FciRR6n59RNm1GRDKfElkUyU4AVSom3Up9UuWPofbx I0RjYrHcoOyaPy7t3gwllijfsy01RICxsAQbnCYWFtN+XeGfeNFQasyzualj/7fK Xe8nLywHoYMqfkIeogO9LTBUsRmO9Mk05QEVAAGdM9o3JoHZVR+u1Sc05CvCHPp/ wMiIYUOWzmLzpdhdWq9OqzIVr4fAhnrpI9Iz8gcfljCA7DQp9kboQRSPocJM6KRB mvM0AiNenrcEBLExUmjC =Gu1v -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180301' into staging target-arm queue: * update MAINTAINERS for Alistair's new email address * add Arm v8.2 FP16 arithmetic extension for linux-user * implement display connector emulation for vexpress board * xilinx_spips: Enable only two slaves when reading/writing with stripe * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands * hw: register: Run post_write hook on reset # gpg: Signature made Thu 01 Mar 2018 11:22:46 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180301: (42 commits) MAINTAINERS: Update my email address linux-user: Report AArch64 FP16 support via hwcap bits target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU arm/translate-a64: add all single op FP16 to handle_fp_1src_half arm/translate-a64: implement simd_scalar_three_reg_same_fp16 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise arm/translate-a64: add FP16 FMOV to simd_mod_imm arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 arm/helper.c: re-factor rsqrte and add rsqrte_f16 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FRECPE arm/helper.c: re-factor recpe and add recepe_f16 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 arm/translate-a64: initial decode for simd_two_reg_misc_fp16 arm/translate-a64: add FP16 x2 ops for simd_indexed ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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9pfs | ||
acpi | ||
adc | ||
alpha | ||
arm | ||
audio | ||
block | ||
bt | ||
char | ||
core | ||
cpu | ||
cris | ||
display | ||
dma | ||
gpio | ||
hppa | ||
i2c | ||
i386 | ||
ide | ||
input | ||
intc | ||
ipack | ||
ipmi | ||
isa | ||
lm32 | ||
m68k | ||
mem | ||
microblaze | ||
mips | ||
misc | ||
moxie | ||
net | ||
nios2 | ||
nvram | ||
openrisc | ||
pci | ||
pci-bridge | ||
pci-host | ||
pcmcia | ||
ppc | ||
rdma | ||
s390x | ||
scsi | ||
sd | ||
sh4 | ||
smbios | ||
sparc | ||
sparc64 | ||
ssi | ||
timer | ||
tpm | ||
tricore | ||
unicore32 | ||
usb | ||
vfio | ||
virtio | ||
watchdog | ||
xen | ||
xenpv | ||
xtensa | ||
Makefile.objs |