Alistair Francis a06fded82e hw/riscv: opentitan: Expose the resetvec as a SoC property ... On the OpenTitan hardware the resetvec is fixed at the start of ROM. In QEMU we don't run the ROM code and instead just jump to the next stage. This means we need to be a little more flexible about what the resetvec is. This patch allows us to set the resetvec from the command line with something like this: -global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400 This way as the next stage changes we can update the resetvec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220914101108.82571-4-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-09-27 07:04:38 +10:00
..
boot.c	hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()	2022-09-07 09:18:33 +02:00
Kconfig	hw/riscv: Enable TPM backends	2022-04-29 10:48:48 +10:00
meson.build	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	2021-07-20 15:32:49 +02:00
microchip_pfsoc.c	hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals	2022-09-07 09:18:33 +02:00
numa.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
opentitan.c	hw/riscv: opentitan: Expose the resetvec as a SoC property	2022-09-27 07:04:38 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()	2022-09-07 09:18:33 +02:00
sifive_e.c	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	2022-05-24 10:38:50 +10:00
sifive_u.c	hw/riscv/sifive_u: Resolve redundant property accessors	2022-05-24 10:38:50 +10:00
spike.c	hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()	2022-09-07 09:18:33 +02:00
virt.c	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00