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xemu/target
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Richard Henderson 9fd46c8362 target/arm: Rewrite helper_sve_st[1234]*_r 
This fixes the endianness problem for softmmu, and moves the
main loop out of a macro and into an inlined function.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181005175350.30752-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-08 14:55:03 +01:00
..
alpha
tcg: Pass tb and index to tcg_gen_exit_tb separately
2018-06-01 15:15:27 -07:00
arm
target/arm: Rewrite helper_sve_st[1234]*_r
2018-10-08 14:55:03 +01:00
cris
tcg-next queue
2018-06-04 11:28:31 +01:00
hppa
tcg-next queue
2018-06-04 11:28:31 +01:00
i386
target/i386: fix translation for icount mode
2018-10-02 19:09:13 +02:00
lm32
tcg-next queue
2018-06-04 11:28:31 +01:00
m68k
target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn
2018-06-11 12:43:42 +02:00
microblaze
target-microblaze: Rework NOP/zero instruction handling
2018-06-15 09:05:00 +02:00
mips
target/mips: Add definition of nanoMIPS I7200 CPU
2018-08-24 17:51:59 +02:00
moxie
tcg-next queue
2018-06-04 11:28:31 +01:00
nios2
tcg-next queue
2018-06-04 11:28:31 +01:00
openrisc
target/openrisc: Fix writes to interrupt mask register
2018-07-03 22:40:33 +09:00
ppc
target/ppc/cpu-models: Re-group the 970 CPUs together again
2018-09-25 11:12:25 +10:00
riscv
riscv: remove define cpu_init()
2018-09-05 09:58:38 -07:00
s390x
s390x/tcg: refactor specification checking
2018-10-04 10:32:39 +02:00
sh4
sh4: fix use_icount with linux-user
2018-08-20 00:11:06 +02:00
sparc
SPARC64: add icount support
2018-06-17 11:13:06 +01:00
tilegx
tcg-next queue
2018-06-04 11:28:31 +01:00
tricore
tcg: Pass tb and index to tcg_gen_exit_tb separately
2018-06-01 15:15:27 -07:00
unicore32
tcg: Pass tb and index to tcg_gen_exit_tb separately
2018-06-01 15:15:27 -07:00
xtensa
target/xtensa: extract gen_check_interrupts call
2018-10-01 11:08:36 -07:00