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1983057470
This controller is also present in i.MX5X devices but they are not yet emulated by QEMU. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
74 lines
1.7 KiB
C
74 lines
1.7 KiB
C
/*
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* IMX6 System Reset Controller
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*
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* Copyright (C) 2012 NICTA
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef IMX6_SRC_H
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#define IMX6_SRC_H
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#include "hw/sysbus.h"
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#include "qemu/bitops.h"
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#define SRC_SCR 0
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#define SRC_SBMR1 1
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#define SRC_SRSR 2
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#define SRC_SISR 5
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#define SRC_SIMR 6
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#define SRC_SBMR2 7
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#define SRC_GPR1 8
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#define SRC_GPR2 9
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#define SRC_GPR3 10
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#define SRC_GPR4 11
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#define SRC_GPR5 12
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#define SRC_GPR6 13
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#define SRC_GPR7 14
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#define SRC_GPR8 15
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#define SRC_GPR9 16
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#define SRC_GPR10 17
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#define SRC_MAX 18
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/* SRC_SCR */
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#define CORE3_ENABLE_SHIFT 24
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#define CORE3_ENABLE_LENGTH 1
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#define CORE2_ENABLE_SHIFT 23
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#define CORE2_ENABLE_LENGTH 1
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#define CORE1_ENABLE_SHIFT 22
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#define CORE1_ENABLE_LENGTH 1
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#define CORE3_RST_SHIFT 16
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#define CORE3_RST_LENGTH 1
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#define CORE2_RST_SHIFT 15
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#define CORE2_RST_LENGTH 1
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#define CORE1_RST_SHIFT 14
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#define CORE1_RST_LENGTH 1
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#define CORE0_RST_SHIFT 13
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#define CORE0_RST_LENGTH 1
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#define SW_IPU1_RST_SHIFT 3
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#define SW_IPU1_RST_LENGTH 1
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#define SW_IPU2_RST_SHIFT 12
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#define SW_IPU2_RST_LENGTH 1
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#define WARM_RST_ENABLE_SHIFT 0
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#define WARM_RST_ENABLE_LENGTH 1
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#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
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#define TYPE_IMX6_SRC "imx6.src"
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#define IMX6_SRC(obj) OBJECT_CHECK(IMX6SRCState, (obj), TYPE_IMX6_SRC)
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typedef struct IMX6SRCState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion iomem;
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uint32_t regs[SRC_MAX];
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} IMX6SRCState;
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#endif /* IMX6_SRC_H */
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