Andrew Jeffery f55d613bc9 watchdog: wdt_aspeed: Add support for the reset width register ... The reset width register controls how the pulse on the SoC's WDTRST{1,2} pins behaves. A pulse is emitted if the external reset bit is set in WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns to configure push-pull/open-drain and active-high/active-low behaviours and thus needs some special handling in the write path. As some of the capabilities depend on the SoC version a silicon-rev property is introduced, which is used to guard version-specific behaviour. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2017-09-04 15:21:54 +01:00
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wdt_aspeed.h	watchdog: wdt_aspeed: Add support for the reset width register	2017-09-04 15:21:54 +01:00
wdt_diag288.h	Clean up decorations and whitespace around header guards	2016-07-12 16:20:46 +02:00