Craig Janeczek a35723f4ce target/mips: Add bit encoding for MXU operand getting pattern 'optn2' ...

Add bit encoding for MXU operand getting pattern 'optn2'.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>

2018-10-29 14:13:47 +01:00

..

cp0_timer.c

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cpu-qom.h

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cpu.c

target/mips: Add disassembler support for nanoMIPS

2018-10-25 22:13:33 +02:00

cpu.h

target/mips: Introduce MXU registers

2018-10-29 14:13:47 +01:00

dsp_helper.c

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gdbstub.c

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helper.c

target/mips: Implement hardware page table walker for MIPS32

2018-10-18 20:37:20 +02:00

helper.h

target/mips: Add CP0 PWCtl register

2018-10-18 20:37:20 +02:00

internal.h

target/mips: Implement hardware page table walker for MIPS32

2018-10-18 20:37:20 +02:00

kvm_mips.h

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kvm.c

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lmi_helper.c

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machine.c

target/mips: Add CP0 PWCtl register

2018-10-18 20:37:20 +02:00

Makefile.objs

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mips-defs.h

target/mips: Define a bit for MXU in insn_flags

2018-10-29 14:13:47 +01:00

mips-semi.c

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msa_helper.c

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op_helper.c

target/mips: Implement hardware page table walker for MIPS32

2018-10-18 20:37:20 +02:00

TODO

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trace-events

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translate_init.inc.c

target/mips: Define the R5900 CPU

2018-10-24 15:20:31 +02:00

translate.c

target/mips: Add bit encoding for MXU operand getting pattern 'optn2'

2018-10-29 14:13:47 +01:00