Wilfred Mallawa aecabd50b7 hw: riscv: opentitan: fixup SPI addresses ...

This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
base addresses. Also adds these as unimplemented devices.

The address references can be found [1].

[1] 6c317992fb/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h (L107)

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220218063839.405082-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2022-03-03 13:14:50 +10:00

..

boot.c

target/riscv: Support start kernel directly by KVM

2022-01-21 15:52:56 +10:00

Kconfig

hw/riscv: virt: Add optional AIA IMSIC support to virt machine

2022-03-03 13:14:50 +10:00

meson.build

…

microchip_pfsoc.c

hw/riscv: Use error_fatal for SoC realisation

2022-01-08 15:46:09 +10:00

numa.c

…

opentitan.c

hw: riscv: opentitan: fixup SPI addresses

2022-03-03 13:14:50 +10:00

riscv_hart.c

…

shakti_c.c

hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

sifive_e.c

hw/riscv: Use error_fatal for SoC realisation

2022-01-08 15:46:09 +10:00

sifive_u.c

hw/riscv: Use error_fatal for SoC realisation

2022-01-08 15:46:09 +10:00

spike.c

hw/riscv: Remove macros for ELF BIOS image names

2022-01-21 15:52:57 +10:00

virt.c

hw/riscv: virt: Increase maximum number of allowed CPUs

2022-03-03 13:14:50 +10:00