ths 16c00cb2c2 Restart interrupts after an exception. ...

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2664 c046a42c-6fe2-441c-8c8c-71466251a162

2007-04-14 12:56:46 +00:00

..

cpu.h

Unify IRQ handling.

2007-04-07 18:14:41 +00:00

exec.h

Actually enable 64bit configuration.

2007-04-01 12:36:18 +00:00

fop_template.c

Preliminiary MIPS64 support, disabled by default due to performance impact.

2006-12-21 01:19:56 +00:00

helper.c

Another fix for CP0 Cause register handling.

2007-04-13 20:17:54 +00:00

mips-defs.h

Throw RI for invalid MFMC0-class instructions. Introduce optional

2007-04-11 02:24:14 +00:00

op_helper_mem.c

Actually enable 64bit configuration.

2007-04-01 12:36:18 +00:00

op_helper.c

Nicer Log formatting.

2007-04-13 22:30:36 +00:00

op_mem.c

Catch unaligned sc/scd.

2007-04-09 14:14:21 +00:00

op_template.c

Preliminiary MIPS64 support, disabled by default due to performance impact.

2006-12-21 01:19:56 +00:00

op.c

Restart interrupts after an exception.

2007-04-14 12:56:46 +00:00

TODO

Update mips TODO.

2007-03-30 18:56:19 +00:00

translate_init.c

Make SYNCI_Step and CCRes CPU-specific.

2007-04-11 20:34:23 +00:00

translate.c

Restart interrupts after an exception.

2007-04-14 12:56:46 +00:00