Yongbok Kim 99029be1c2 target/mips: Add implementation of GINVT instruction ...

Implement emulation of GINVT instruction. As QEMU doesn't support
caches and virtualization, this implementation covers only one
instruction (GINVT - Global Invalidate TLB) among all TLB-related
MIPS instructions.

Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>

2020-01-29 19:28:52 +01:00

..

libvixl

libvixl: remove per-target compiler flags

2019-12-17 19:32:48 +01:00

alpha.c

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arm-a64.cc

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arm.c

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cris.c

cris: do not leak struct cris_disasm_data

2019-10-04 18:49:17 +02:00

hppa.c

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i386.c

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lm32.c

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m68k.c

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Makefile.objs

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microblaze.c

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mips.c

target/mips: Add implementation of GINVT instruction

2020-01-29 19:28:52 +01:00

moxie.c

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nanomips.cpp

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nanomips.h

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nios2.c

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ppc.c

ppc: Add support for 'mffsl' instruction

2019-08-21 17:17:39 +10:00

riscv.c

disas/riscv: Fix rdinstreth constraint

2019-06-27 02:47:04 -07:00

s390.c

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sh4.c

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sparc.c

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tci.c

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xtensa.c

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