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ae2474f118
Change the iMX-SoC based boards to use the new boot.c functionality to allow us to enable psci-conduit only if the guest is being booted in EL1 or EL2, so that if the user runs guest EL3 firmware code our PSCI emulation doesn't get in its way. To do this we stop setting the psci-conduit property on the CPU objects in the SoC code, and instead set the psci_conduit field in the arm_boot_info struct to tell the common boot loader code that we'd like PSCI if the guest is starting at an EL that it makes sense with. This affects the mcimx6ul-evk and mcimx7d-sabre boards. Note that for the mcimx7d board, this means that when running guest code at EL3 there is currently no way to power on the secondary CPUs, because we do not currently have a model of the system reset controller module which should be used to do that for the imx7 SoC, only for the imx6 SoC. (Previously EL3 code which knew it was running on QEMU could use a PSCI call to do this.) This doesn't affect the imx6ul-evk board because it is uniprocessor. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Cédric Le Goater <clg@kaod.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220127154639.2090164-5-peter.maydell@linaro.org
77 lines
2.2 KiB
C
77 lines
2.2 KiB
C
/*
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* Copyright (c) 2018, Impinj, Inc.
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*
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* MCIMX7D_SABRE Board System emulation.
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This code is licensed under the GPL, version 2 or later.
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* See the file `COPYING' in the top level directory.
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*
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* It (partially) emulates a mcimx7d_sabre board, with a Freescale
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* i.MX7 SoC
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/arm/fsl-imx7.h"
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#include "hw/boards.h"
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#include "hw/qdev-properties.h"
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#include "qemu/error-report.h"
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#include "sysemu/qtest.h"
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static void mcimx7d_sabre_init(MachineState *machine)
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{
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static struct arm_boot_info boot_info;
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FslIMX7State *s;
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int i;
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if (machine->ram_size > FSL_IMX7_MMDC_SIZE) {
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error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
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machine->ram_size, FSL_IMX7_MMDC_SIZE);
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exit(1);
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}
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boot_info = (struct arm_boot_info) {
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.loader_start = FSL_IMX7_MMDC_ADDR,
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.board_id = -1,
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.ram_size = machine->ram_size,
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.nb_cpus = machine->smp.cpus,
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.psci_conduit = QEMU_PSCI_CONDUIT_SMC,
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};
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s = FSL_IMX7(object_new(TYPE_FSL_IMX7));
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object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
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qdev_realize(DEVICE(s), NULL, &error_fatal);
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memory_region_add_subregion(get_system_memory(), FSL_IMX7_MMDC_ADDR,
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machine->ram);
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for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
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BusState *bus;
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DeviceState *carddev;
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DriveInfo *di;
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BlockBackend *blk;
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di = drive_get(IF_SD, 0, i);
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blk = di ? blk_by_legacy_dinfo(di) : NULL;
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bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus");
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carddev = qdev_new(TYPE_SD_CARD);
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qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
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qdev_realize_and_unref(carddev, bus, &error_fatal);
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}
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if (!qtest_enabled()) {
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arm_load_kernel(&s->cpu[0], machine, &boot_info);
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}
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}
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static void mcimx7d_sabre_machine_init(MachineClass *mc)
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{
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mc->desc = "Freescale i.MX7 DUAL SABRE (Cortex-A7)";
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mc->init = mcimx7d_sabre_init;
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mc->max_cpus = FSL_IMX7_NUM_CPUS;
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mc->default_ram_id = "mcimx7d-sabre.ram";
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}
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DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init)
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