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bf7ca80386
Test that when we change the scaling of the system counter that the system timer responds appropriately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
241 lines
8.3 KiB
C
241 lines
8.3 KiB
C
/*
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* QTest testcase for the SSE timer device
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*
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* Copyright (c) 2021 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "libqtest-single.h"
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/*
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* SSE-123/SSE-300 timer in the mps3-an547 board, where it is driven
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* at 32MHz, so 31.25ns per tick.
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*/
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#define TIMER_BASE 0x48000000
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/* PERIPHNSPPC0 register in the SSE-300 Secure Access Configuration block */
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#define PERIPHNSPPC0 (0x50080000 + 0x70)
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/* Base of the System Counter control frame */
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#define COUNTER_BASE 0x58100000
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/* SSE counter register offsets in the control frame */
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#define CNTCR 0
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#define CNTSR 0x4
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#define CNTCV_LO 0x8
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#define CNTCV_HI 0xc
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#define CNTSCR 0x10
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/* SSE timer register offsets */
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#define CNTPCT_LO 0
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#define CNTPCT_HI 4
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#define CNTFRQ 0x10
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#define CNTP_CVAL_LO 0x20
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#define CNTP_CVAL_HI 0x24
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#define CNTP_TVAL 0x28
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#define CNTP_CTL 0x2c
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#define CNTP_AIVAL_LO 0x40
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#define CNTP_AIVAL_HI 0x44
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#define CNTP_AIVAL_RELOAD 0x48
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#define CNTP_AIVAL_CTL 0x4c
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/* 4 ticks in nanoseconds (so we can work in integers) */
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#define FOUR_TICKS 125
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static void clock_step_ticks(uint64_t ticks)
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{
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/*
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* Advance the qtest clock by however many nanoseconds we
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* need to move the timer forward the specified number of ticks.
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* ticks must be a multiple of 4, so we get a whole number of ns.
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*/
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assert(!(ticks & 3));
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clock_step(FOUR_TICKS * (ticks >> 2));
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}
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static void reset_counter_and_timer(void)
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{
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/*
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* Reset the system counter and the timer between tests. This
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* isn't a full reset, but it's sufficient for what the tests check.
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*/
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writel(COUNTER_BASE + CNTCR, 0);
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writel(TIMER_BASE + CNTP_CTL, 0);
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writel(TIMER_BASE + CNTP_AIVAL_CTL, 0);
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writel(COUNTER_BASE + CNTCV_LO, 0);
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writel(COUNTER_BASE + CNTCV_HI, 0);
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}
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static void test_counter(void)
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{
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/* Basic counter functionality test */
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reset_counter_and_timer();
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/* The counter should start disabled: check that it doesn't move */
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clock_step_ticks(100);
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g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 0);
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g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0);
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/* Now enable it and check that it does count */
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writel(COUNTER_BASE + CNTCR, 1);
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clock_step_ticks(100);
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g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 100);
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g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0);
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/* Check the counter scaling functionality */
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writel(COUNTER_BASE + CNTCR, 0);
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writel(COUNTER_BASE + CNTSCR, 0x00100000); /* 1/16th normal speed */
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writel(COUNTER_BASE + CNTCR, 5); /* EN, SCEN */
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clock_step_ticks(160);
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g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 110);
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g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0);
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}
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static void test_timer(void)
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{
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/* Basic timer functionality test */
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reset_counter_and_timer();
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/*
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* The timer is behind a Peripheral Protection Controller, and
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* qtest accesses are always non-secure (no memory attributes),
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* so we must program the PPC to accept NS transactions. TIMER0
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* is on port 0 of PPC0, controlled by bit 0 of this register.
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*/
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writel(PERIPHNSPPC0, 1);
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/* We must enable the System Counter or the timer won't run. */
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writel(COUNTER_BASE + CNTCR, 1);
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/* Timer starts disabled and with a counter of 0 */
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 0);
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g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), ==, 0);
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g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), ==, 0);
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/* Turn it on */
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writel(TIMER_BASE + CNTP_CTL, 1);
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/* Is the timer ticking? */
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clock_step_ticks(100);
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g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), ==, 100);
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g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), ==, 0);
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/* Set the CompareValue to 4000 ticks */
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writel(TIMER_BASE + CNTP_CVAL_LO, 4000);
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writel(TIMER_BASE + CNTP_CVAL_HI, 0);
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/* Check TVAL view of the counter */
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_TVAL), ==, 3900);
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/* Advance to the CompareValue mark and check ISTATUS is set */
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clock_step_ticks(3900);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_TVAL), ==, 0);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
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/* Now exercise the auto-reload part of the timer */
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writel(TIMER_BASE + CNTP_AIVAL_RELOAD, 200);
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writel(TIMER_BASE + CNTP_AIVAL_CTL, 1);
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/* Check AIVAL was reloaded and that ISTATUS is now clear */
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), ==, 4200);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
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/*
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* Check that when we advance forward to the reload time the interrupt
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* fires and the value reloads
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*/
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clock_step_ticks(100);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
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clock_step_ticks(100);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), ==, 4400);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0);
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clock_step_ticks(100);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
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/* Check that writing 0 to CLR clears the interrupt */
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writel(TIMER_BASE + CNTP_AIVAL_CTL, 1);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
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/* Check that when we move forward to the reload time it fires again */
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clock_step_ticks(100);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), ==, 4600);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0);
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/*
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* Step the clock far enough that we overflow the low half of the
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* CNTPCT and AIVAL registers, and check that their high halves
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* give the right values. We do the forward movement in
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* non-autoinc mode because otherwise it takes forever as the
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* timer has to emulate all the 'reload at t + N, t + 2N, etc'
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* steps.
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*/
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writel(TIMER_BASE + CNTP_AIVAL_CTL, 0);
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clock_step_ticks(0x42ULL << 32);
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g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), ==, 4400);
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g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), ==, 0x42);
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/* Turn on the autoinc again to check AIVAL_HI */
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writel(TIMER_BASE + CNTP_AIVAL_CTL, 1);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), ==, 4600);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0x42);
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}
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static void test_timer_scale_change(void)
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{
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/*
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* Test that the timer responds correctly to counter
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* scaling changes while it has an active timer.
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*/
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reset_counter_and_timer();
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/* Give ourselves access to the timer, and enable the counter and timer */
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writel(PERIPHNSPPC0, 1);
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writel(COUNTER_BASE + CNTCR, 1);
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writel(TIMER_BASE + CNTP_CTL, 1);
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/* Set the CompareValue to 4000 ticks */
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writel(TIMER_BASE + CNTP_CVAL_LO, 4000);
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writel(TIMER_BASE + CNTP_CVAL_HI, 0);
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/* Advance halfway and check ISTATUS is not set */
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clock_step_ticks(2000);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
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/* Reprogram the counter to run at 1/16th speed */
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writel(COUNTER_BASE + CNTCR, 0);
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writel(COUNTER_BASE + CNTSCR, 0x00100000); /* 1/16th normal speed */
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writel(COUNTER_BASE + CNTCR, 5); /* EN, SCEN */
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/* Advance to where the timer would have fired and check it has not */
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clock_step_ticks(2000);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
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/* Advance to where the timer must fire at the new clock rate */
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clock_step_ticks(29996);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
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clock_step_ticks(4);
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g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
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}
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int main(int argc, char **argv)
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{
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int r;
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g_test_init(&argc, &argv, NULL);
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qtest_start("-machine mps3-an547");
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qtest_add_func("/sse-timer/counter", test_counter);
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qtest_add_func("/sse-timer/timer", test_timer);
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qtest_add_func("/sse-timer/timer-scale-change", test_timer_scale_change);
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r = g_test_run();
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qtest_end();
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return r;
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}
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