Alexander Wagner d11e316d84 hw/riscv: Fix OT IBEX reset vector ...

The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".

[1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2021-05-11 20:02:07 +10:00

..

boot.c

riscv: Pass RISCVHartArrayState by pointer

2021-01-16 14:34:46 -08:00

Kconfig

hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine

2021-05-11 20:02:06 +10:00

meson.build

riscv: Add initial support for Shakti C machine

2021-05-11 20:01:38 +10:00

microchip_pfsoc.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

numa.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

opentitan.c

hw/riscv: Fix OT IBEX reset vector

2021-05-11 20:02:07 +10:00

riscv_hart.c

…

shakti_c.c

hw/riscv: Connect Shakti UART to Shakti platform

2021-05-11 20:02:06 +10:00

sifive_e.c

hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]

2021-05-11 20:01:10 +10:00

sifive_u.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

spike.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

virt.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00