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2507c12ab0
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
614 lines
14 KiB
C
614 lines
14 KiB
C
/*
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* QEMU ETRAX Ethernet Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include "hw.h"
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#include "net.h"
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#include "etraxfs.h"
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#define D(x)
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/* Advertisement control register. */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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/*
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* The MDIO extensions in the TDK PHY model were reversed engineered from the
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* linux driver (PHYID and Diagnostics reg).
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* TODO: Add friendly names for the register nums.
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*/
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struct qemu_phy
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{
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uint32_t regs[32];
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int link;
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unsigned int (*read)(struct qemu_phy *phy, unsigned int req);
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void (*write)(struct qemu_phy *phy, unsigned int req,
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unsigned int data);
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};
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static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req)
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{
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int regnum;
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unsigned r = 0;
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regnum = req & 0x1f;
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switch (regnum) {
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case 1:
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if (!phy->link)
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break;
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/* MR1. */
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/* Speeds and modes. */
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r |= (1 << 13) | (1 << 14);
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r |= (1 << 11) | (1 << 12);
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r |= (1 << 5); /* Autoneg complete. */
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r |= (1 << 3); /* Autoneg able. */
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r |= (1 << 2); /* link. */
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break;
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case 5:
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/* Link partner ability.
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We are kind; always agree with whatever best mode
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the guest advertises. */
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r = 1 << 14; /* Success. */
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/* Copy advertised modes. */
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r |= phy->regs[4] & (15 << 5);
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/* Autoneg support. */
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r |= 1;
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break;
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case 18:
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{
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/* Diagnostics reg. */
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int duplex = 0;
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int speed_100 = 0;
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if (!phy->link)
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break;
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/* Are we advertising 100 half or 100 duplex ? */
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speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
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speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
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/* Are we advertising 10 duplex or 100 duplex ? */
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duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
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duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
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r = (speed_100 << 10) | (duplex << 11);
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}
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break;
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default:
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r = phy->regs[regnum];
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break;
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}
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D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum));
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return r;
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}
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static void
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tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data)
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{
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int regnum;
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regnum = req & 0x1f;
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D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
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switch (regnum) {
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default:
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phy->regs[regnum] = data;
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break;
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}
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}
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static void
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tdk_init(struct qemu_phy *phy)
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{
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phy->regs[0] = 0x3100;
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/* PHY Id. */
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phy->regs[2] = 0x0300;
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phy->regs[3] = 0xe400;
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/* Autonegotiation advertisement reg. */
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phy->regs[4] = 0x01E1;
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phy->link = 1;
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phy->read = tdk_read;
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phy->write = tdk_write;
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}
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struct qemu_mdio
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{
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/* bus. */
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int mdc;
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int mdio;
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/* decoder. */
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enum {
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PREAMBLE,
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SOF,
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OPC,
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ADDR,
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REQ,
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TURNAROUND,
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DATA
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} state;
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unsigned int drive;
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unsigned int cnt;
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unsigned int addr;
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unsigned int opc;
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unsigned int req;
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unsigned int data;
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struct qemu_phy *devs[32];
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};
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static void
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mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)
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{
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bus->devs[addr & 0x1f] = phy;
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}
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#ifdef USE_THIS_DEAD_CODE
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static void
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mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)
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{
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bus->devs[addr & 0x1f] = NULL;
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}
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#endif
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static void mdio_read_req(struct qemu_mdio *bus)
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{
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struct qemu_phy *phy;
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phy = bus->devs[bus->addr];
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if (phy && phy->read)
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bus->data = phy->read(phy, bus->req);
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else
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bus->data = 0xffff;
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}
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static void mdio_write_req(struct qemu_mdio *bus)
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{
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struct qemu_phy *phy;
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phy = bus->devs[bus->addr];
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if (phy && phy->write)
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phy->write(phy, bus->req, bus->data);
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}
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static void mdio_cycle(struct qemu_mdio *bus)
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{
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bus->cnt++;
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D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
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bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive));
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#if 0
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if (bus->mdc)
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printf("%d", bus->mdio);
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#endif
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switch (bus->state)
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{
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case PREAMBLE:
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if (bus->mdc) {
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if (bus->cnt >= (32 * 2) && !bus->mdio) {
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bus->cnt = 0;
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bus->state = SOF;
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bus->data = 0;
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}
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}
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break;
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case SOF:
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if (bus->mdc) {
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if (bus->mdio != 1)
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printf("WARNING: no SOF\n");
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if (bus->cnt == 1*2) {
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bus->cnt = 0;
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bus->opc = 0;
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bus->state = OPC;
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}
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}
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break;
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case OPC:
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if (bus->mdc) {
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bus->opc <<= 1;
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bus->opc |= bus->mdio & 1;
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if (bus->cnt == 2*2) {
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bus->cnt = 0;
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bus->addr = 0;
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bus->state = ADDR;
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}
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}
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break;
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case ADDR:
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if (bus->mdc) {
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bus->addr <<= 1;
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bus->addr |= bus->mdio & 1;
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if (bus->cnt == 5*2) {
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bus->cnt = 0;
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bus->req = 0;
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bus->state = REQ;
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}
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}
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break;
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case REQ:
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if (bus->mdc) {
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bus->req <<= 1;
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bus->req |= bus->mdio & 1;
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if (bus->cnt == 5*2) {
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bus->cnt = 0;
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bus->state = TURNAROUND;
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}
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}
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break;
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case TURNAROUND:
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if (bus->mdc && bus->cnt == 2*2) {
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bus->mdio = 0;
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bus->cnt = 0;
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if (bus->opc == 2) {
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bus->drive = 1;
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mdio_read_req(bus);
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bus->mdio = bus->data & 1;
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}
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bus->state = DATA;
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}
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break;
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case DATA:
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if (!bus->mdc) {
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if (bus->drive) {
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bus->mdio = !!(bus->data & (1 << 15));
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bus->data <<= 1;
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}
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} else {
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if (!bus->drive) {
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bus->data <<= 1;
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bus->data |= bus->mdio;
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}
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if (bus->cnt == 16 * 2) {
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bus->cnt = 0;
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bus->state = PREAMBLE;
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if (!bus->drive)
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mdio_write_req(bus);
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bus->drive = 0;
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}
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}
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break;
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default:
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break;
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}
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}
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/* ETRAX-FS Ethernet MAC block starts here. */
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#define RW_MA0_LO 0x00
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#define RW_MA0_HI 0x01
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#define RW_MA1_LO 0x02
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#define RW_MA1_HI 0x03
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#define RW_GA_LO 0x04
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#define RW_GA_HI 0x05
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#define RW_GEN_CTRL 0x06
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#define RW_REC_CTRL 0x07
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#define RW_TR_CTRL 0x08
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#define RW_CLR_ERR 0x09
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#define RW_MGM_CTRL 0x0a
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#define R_STAT 0x0b
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#define FS_ETH_MAX_REGS 0x17
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struct fs_eth
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{
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NICState *nic;
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NICConf conf;
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int ethregs;
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/* Two addrs in the filter. */
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uint8_t macaddr[2][6];
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uint32_t regs[FS_ETH_MAX_REGS];
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struct etraxfs_dma_client *dma_out;
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struct etraxfs_dma_client *dma_in;
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/* MDIO bus. */
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struct qemu_mdio mdio_bus;
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unsigned int phyaddr;
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int duplex_mismatch;
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/* PHY. */
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struct qemu_phy phy;
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};
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static void eth_validate_duplex(struct fs_eth *eth)
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{
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struct qemu_phy *phy;
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unsigned int phy_duplex;
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unsigned int mac_duplex;
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int new_mm = 0;
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phy = eth->mdio_bus.devs[eth->phyaddr];
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phy_duplex = !!(phy->read(phy, 18) & (1 << 11));
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mac_duplex = !!(eth->regs[RW_REC_CTRL] & 128);
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if (mac_duplex != phy_duplex)
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new_mm = 1;
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if (eth->regs[RW_GEN_CTRL] & 1) {
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if (new_mm != eth->duplex_mismatch) {
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if (new_mm)
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printf("HW: WARNING "
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"ETH duplex mismatch MAC=%d PHY=%d\n",
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mac_duplex, phy_duplex);
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else
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printf("HW: ETH duplex ok.\n");
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}
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eth->duplex_mismatch = new_mm;
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}
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}
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static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
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{
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struct fs_eth *eth = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_STAT:
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r = eth->mdio_bus.mdio & 1;
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break;
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default:
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r = eth->regs[addr];
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D(printf ("%s %x\n", __func__, addr * 4));
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break;
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}
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return r;
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}
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static void eth_update_ma(struct fs_eth *eth, int ma)
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{
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int reg;
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int i = 0;
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ma &= 1;
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reg = RW_MA0_LO;
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if (ma)
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reg = RW_MA1_LO;
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eth->macaddr[ma][i++] = eth->regs[reg];
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eth->macaddr[ma][i++] = eth->regs[reg] >> 8;
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eth->macaddr[ma][i++] = eth->regs[reg] >> 16;
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eth->macaddr[ma][i++] = eth->regs[reg] >> 24;
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eth->macaddr[ma][i++] = eth->regs[reg + 1];
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eth->macaddr[ma][i] = eth->regs[reg + 1] >> 8;
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D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma,
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eth->macaddr[ma][0], eth->macaddr[ma][1],
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eth->macaddr[ma][2], eth->macaddr[ma][3],
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eth->macaddr[ma][4], eth->macaddr[ma][5]));
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}
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static void
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eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct fs_eth *eth = opaque;
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addr >>= 2;
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switch (addr)
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{
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case RW_MA0_LO:
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case RW_MA0_HI:
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eth->regs[addr] = value;
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eth_update_ma(eth, 0);
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break;
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case RW_MA1_LO:
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case RW_MA1_HI:
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eth->regs[addr] = value;
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eth_update_ma(eth, 1);
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break;
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case RW_MGM_CTRL:
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/* Attach an MDIO/PHY abstraction. */
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if (value & 2)
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eth->mdio_bus.mdio = value & 1;
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if (eth->mdio_bus.mdc != (value & 4)) {
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mdio_cycle(ð->mdio_bus);
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eth_validate_duplex(eth);
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}
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eth->mdio_bus.mdc = !!(value & 4);
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eth->regs[addr] = value;
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break;
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case RW_REC_CTRL:
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eth->regs[addr] = value;
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eth_validate_duplex(eth);
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break;
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default:
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eth->regs[addr] = value;
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D(printf ("%s %x %x\n",
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__func__, addr, value));
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break;
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}
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}
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/* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
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filter dropping group addresses we have not joined. The filter has 64
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bits (m). The has function is a simple nible xor of the group addr. */
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static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa)
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{
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unsigned int hsh;
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int m_individual = eth->regs[RW_REC_CTRL] & 4;
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int match;
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/* First bit on the wire of a MAC address signals multicast or
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physical address. */
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if (!m_individual && !(sa[0] & 1))
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return 0;
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/* Calculate the hash index for the GA registers. */
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hsh = 0;
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hsh ^= (*sa) & 0x3f;
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hsh ^= ((*sa) >> 6) & 0x03;
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++sa;
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hsh ^= ((*sa) << 2) & 0x03c;
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hsh ^= ((*sa) >> 4) & 0xf;
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++sa;
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hsh ^= ((*sa) << 4) & 0x30;
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hsh ^= ((*sa) >> 2) & 0x3f;
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++sa;
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hsh ^= (*sa) & 0x3f;
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hsh ^= ((*sa) >> 6) & 0x03;
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++sa;
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hsh ^= ((*sa) << 2) & 0x03c;
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hsh ^= ((*sa) >> 4) & 0xf;
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++sa;
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hsh ^= ((*sa) << 4) & 0x30;
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hsh ^= ((*sa) >> 2) & 0x3f;
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hsh &= 63;
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if (hsh > 31)
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match = eth->regs[RW_GA_HI] & (1 << (hsh - 32));
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else
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match = eth->regs[RW_GA_LO] & (1 << hsh);
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D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh,
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eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match));
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return match;
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}
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static int eth_can_receive(VLANClientState *nc)
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{
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return 1;
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}
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static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
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{
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unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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struct fs_eth *eth = DO_UPCAST(NICState, nc, nc)->opaque;
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int use_ma0 = eth->regs[RW_REC_CTRL] & 1;
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int use_ma1 = eth->regs[RW_REC_CTRL] & 2;
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int r_bcast = eth->regs[RW_REC_CTRL] & 8;
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if (size < 12)
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return -1;
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D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
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buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
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use_ma0, use_ma1, r_bcast));
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/* Does the frame get through the address filters? */
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if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6))
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&& (!use_ma1 || memcmp(buf, eth->macaddr[1], 6))
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&& (!r_bcast || memcmp(buf, sa_bcast, 6))
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&& !eth_match_groupaddr(eth, buf))
|
|
return size;
|
|
|
|
/* FIXME: Find another way to pass on the fake csum. */
|
|
etraxfs_dmac_input(eth->dma_in, (void *)buf, size + 4, 1);
|
|
|
|
return size;
|
|
}
|
|
|
|
static int eth_tx_push(void *opaque, unsigned char *buf, int len)
|
|
{
|
|
struct fs_eth *eth = opaque;
|
|
|
|
D(printf("%s buf=%p len=%d\n", __func__, buf, len));
|
|
qemu_send_packet(ð->nic->nc, buf, len);
|
|
return len;
|
|
}
|
|
|
|
static void eth_set_link(VLANClientState *nc)
|
|
{
|
|
struct fs_eth *eth = DO_UPCAST(NICState, nc, nc)->opaque;
|
|
D(printf("%s %d\n", __func__, nc->link_down));
|
|
eth->phy.link = !nc->link_down;
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const eth_read[] = {
|
|
NULL, NULL,
|
|
ð_readl,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const eth_write[] = {
|
|
NULL, NULL,
|
|
ð_writel,
|
|
};
|
|
|
|
static void eth_cleanup(VLANClientState *nc)
|
|
{
|
|
struct fs_eth *eth = DO_UPCAST(NICState, nc, nc)->opaque;
|
|
|
|
cpu_unregister_io_memory(eth->ethregs);
|
|
|
|
qemu_free(eth->dma_out);
|
|
qemu_free(eth);
|
|
}
|
|
|
|
static NetClientInfo net_etraxfs_info = {
|
|
.type = NET_CLIENT_TYPE_NIC,
|
|
.size = sizeof(NICState),
|
|
.can_receive = eth_can_receive,
|
|
.receive = eth_receive,
|
|
.cleanup = eth_cleanup,
|
|
.link_status_changed = eth_set_link,
|
|
};
|
|
|
|
void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr)
|
|
{
|
|
struct etraxfs_dma_client *dma = NULL;
|
|
struct fs_eth *eth = NULL;
|
|
|
|
qemu_check_nic_model(nd, "fseth");
|
|
|
|
dma = qemu_mallocz(sizeof *dma * 2);
|
|
eth = qemu_mallocz(sizeof *eth);
|
|
|
|
dma[0].client.push = eth_tx_push;
|
|
dma[0].client.opaque = eth;
|
|
dma[1].client.opaque = eth;
|
|
dma[1].client.pull = NULL;
|
|
|
|
eth->dma_out = dma;
|
|
eth->dma_in = dma + 1;
|
|
|
|
/* Connect the phy. */
|
|
eth->phyaddr = phyaddr & 0x1f;
|
|
tdk_init(ð->phy);
|
|
mdio_attach(ð->mdio_bus, ð->phy, eth->phyaddr);
|
|
|
|
eth->ethregs = cpu_register_io_memory(eth_read, eth_write, eth,
|
|
DEVICE_NATIVE_ENDIAN);
|
|
cpu_register_physical_memory (base, 0x5c, eth->ethregs);
|
|
|
|
memcpy(eth->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr));
|
|
eth->conf.vlan = nd->vlan;
|
|
eth->conf.peer = nd->netdev;
|
|
|
|
eth->nic = qemu_new_nic(&net_etraxfs_info, ð->conf,
|
|
nd->model, nd->name, eth);
|
|
|
|
return dma;
|
|
}
|