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b4578cd91c
Allow expansion either via shift by scalar or by replicating the scalar for shift by vector. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v3: Use a private structure for do_gvec_shifts.
655 lines
18 KiB
C
655 lines
18 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2018 Linaro, Inc.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "tcg.h"
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#include "tcg-op.h"
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#include "tcg-mo.h"
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/* Reduce the number of ifdefs below. This assumes that all uses of
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TCGV_HIGH and TCGV_LOW are properly protected by a conditional that
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the compiler can eliminate. */
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#if TCG_TARGET_REG_BITS == 64
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extern TCGv_i32 TCGV_LOW_link_error(TCGv_i64);
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extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
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#define TCGV_LOW TCGV_LOW_link_error
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#define TCGV_HIGH TCGV_HIGH_link_error
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#endif
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/*
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* Vector optional opcode tracking.
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* Except for the basic logical operations (and, or, xor), and
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* data movement (mov, ld, st, dupi), many vector opcodes are
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* optional and may not be supported on the host. Thank Intel
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* for the irregularity in their instruction set.
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*
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* The gvec expanders allow custom vector operations to be composed,
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* generally via the .fniv callback in the GVecGen* structures. At
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* the same time, in deciding whether to use this hook we need to
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* know if the host supports the required operations. This is
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* presented as an array of opcodes, terminated by 0. Each opcode
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* is assumed to be expanded with the given VECE.
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*
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* For debugging, we want to validate this array. Therefore, when
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* tcg_ctx->vec_opt_opc is non-NULL, the tcg_gen_*_vec expanders
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* will validate that their opcode is present in the list.
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*/
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#ifdef CONFIG_DEBUG_TCG
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void tcg_assert_listed_vecop(TCGOpcode op)
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{
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const TCGOpcode *p = tcg_ctx->vecop_list;
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if (p) {
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for (; *p; ++p) {
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if (*p == op) {
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return;
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}
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}
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g_assert_not_reached();
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}
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}
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#endif
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bool tcg_can_emit_vecop_list(const TCGOpcode *list,
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TCGType type, unsigned vece)
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{
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if (list == NULL) {
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return true;
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}
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for (; *list; ++list) {
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TCGOpcode opc = *list;
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#ifdef CONFIG_DEBUG_TCG
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switch (opc) {
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case INDEX_op_and_vec:
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case INDEX_op_or_vec:
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case INDEX_op_xor_vec:
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case INDEX_op_mov_vec:
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case INDEX_op_dup_vec:
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case INDEX_op_dupi_vec:
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case INDEX_op_dup2_vec:
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case INDEX_op_ld_vec:
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case INDEX_op_st_vec:
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/* These opcodes are mandatory and should not be listed. */
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g_assert_not_reached();
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default:
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break;
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}
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#endif
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if (tcg_can_emit_vec_op(opc, type, vece)) {
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continue;
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}
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/*
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* The opcode list is created by front ends based on what they
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* actually invoke. We must mirror the logic in the routines
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* below for generic expansions using other opcodes.
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*/
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switch (opc) {
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case INDEX_op_neg_vec:
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if (tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece)) {
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continue;
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}
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break;
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default:
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break;
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}
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return false;
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}
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return true;
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}
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void vec_gen_2(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGArg a)
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{
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TCGOp *op = tcg_emit_op(opc);
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TCGOP_VECL(op) = type - TCG_TYPE_V64;
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TCGOP_VECE(op) = vece;
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op->args[0] = r;
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op->args[1] = a;
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}
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void vec_gen_3(TCGOpcode opc, TCGType type, unsigned vece,
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TCGArg r, TCGArg a, TCGArg b)
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{
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TCGOp *op = tcg_emit_op(opc);
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TCGOP_VECL(op) = type - TCG_TYPE_V64;
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TCGOP_VECE(op) = vece;
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op->args[0] = r;
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op->args[1] = a;
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op->args[2] = b;
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}
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void vec_gen_4(TCGOpcode opc, TCGType type, unsigned vece,
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TCGArg r, TCGArg a, TCGArg b, TCGArg c)
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{
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TCGOp *op = tcg_emit_op(opc);
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TCGOP_VECL(op) = type - TCG_TYPE_V64;
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TCGOP_VECE(op) = vece;
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op->args[0] = r;
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op->args[1] = a;
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op->args[2] = b;
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op->args[3] = c;
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}
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static void vec_gen_op2(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a)
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{
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TCGTemp *rt = tcgv_vec_temp(r);
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TCGTemp *at = tcgv_vec_temp(a);
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TCGType type = rt->base_type;
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/* Must enough inputs for the output. */
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tcg_debug_assert(at->base_type >= type);
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vec_gen_2(opc, type, vece, temp_arg(rt), temp_arg(at));
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}
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static void vec_gen_op3(TCGOpcode opc, unsigned vece,
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TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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TCGTemp *rt = tcgv_vec_temp(r);
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TCGTemp *at = tcgv_vec_temp(a);
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TCGTemp *bt = tcgv_vec_temp(b);
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TCGType type = rt->base_type;
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/* Must enough inputs for the output. */
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tcg_debug_assert(at->base_type >= type);
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tcg_debug_assert(bt->base_type >= type);
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vec_gen_3(opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt));
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}
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void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)
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{
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if (r != a) {
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vec_gen_op2(INDEX_op_mov_vec, 0, r, a);
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}
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}
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#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)
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static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)
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{
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TCGTemp *rt = tcgv_vec_temp(r);
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vec_gen_2(INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a);
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}
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TCGv_vec tcg_const_zeros_vec(TCGType type)
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{
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TCGv_vec ret = tcg_temp_new_vec(type);
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do_dupi_vec(ret, MO_REG, 0);
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return ret;
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}
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TCGv_vec tcg_const_ones_vec(TCGType type)
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{
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TCGv_vec ret = tcg_temp_new_vec(type);
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do_dupi_vec(ret, MO_REG, -1);
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return ret;
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}
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TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec m)
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{
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TCGTemp *t = tcgv_vec_temp(m);
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return tcg_const_zeros_vec(t->base_type);
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}
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TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
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{
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TCGTemp *t = tcgv_vec_temp(m);
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return tcg_const_ones_vec(t->base_type);
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}
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void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
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{
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if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
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do_dupi_vec(r, MO_32, a);
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} else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
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do_dupi_vec(r, MO_64, a);
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} else {
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TCGv_i64 c = tcg_const_i64(a);
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tcg_gen_dup_i64_vec(MO_64, r, c);
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tcg_temp_free_i64(c);
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}
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}
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void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)
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{
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do_dupi_vec(r, MO_REG, dup_const(MO_32, a));
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}
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void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)
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{
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do_dupi_vec(r, MO_REG, dup_const(MO_16, a));
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}
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void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
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{
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do_dupi_vec(r, MO_REG, dup_const(MO_8, a));
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}
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void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
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{
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do_dupi_vec(r, MO_REG, dup_const(vece, a));
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}
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void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
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{
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TCGArg ri = tcgv_vec_arg(r);
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TCGTemp *rt = arg_temp(ri);
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TCGType type = rt->base_type;
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if (TCG_TARGET_REG_BITS == 64) {
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TCGArg ai = tcgv_i64_arg(a);
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vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);
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} else if (vece == MO_64) {
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TCGArg al = tcgv_i32_arg(TCGV_LOW(a));
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TCGArg ah = tcgv_i32_arg(TCGV_HIGH(a));
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vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah);
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} else {
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TCGArg ai = tcgv_i32_arg(TCGV_LOW(a));
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vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);
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}
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}
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void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TCGv_i32 a)
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{
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TCGArg ri = tcgv_vec_arg(r);
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TCGArg ai = tcgv_i32_arg(a);
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TCGTemp *rt = arg_temp(ri);
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TCGType type = rt->base_type;
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vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);
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}
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void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec r, TCGv_ptr b,
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tcg_target_long ofs)
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{
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TCGArg ri = tcgv_vec_arg(r);
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TCGArg bi = tcgv_ptr_arg(b);
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TCGTemp *rt = arg_temp(ri);
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TCGType type = rt->base_type;
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vec_gen_3(INDEX_op_dupm_vec, type, vece, ri, bi, ofs);
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}
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static void vec_gen_ldst(TCGOpcode opc, TCGv_vec r, TCGv_ptr b, TCGArg o)
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{
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TCGArg ri = tcgv_vec_arg(r);
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TCGArg bi = tcgv_ptr_arg(b);
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TCGTemp *rt = arg_temp(ri);
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TCGType type = rt->base_type;
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vec_gen_3(opc, type, 0, ri, bi, o);
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}
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void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr b, TCGArg o)
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{
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vec_gen_ldst(INDEX_op_ld_vec, r, b, o);
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}
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void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr b, TCGArg o)
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{
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vec_gen_ldst(INDEX_op_st_vec, r, b, o);
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}
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void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr b, TCGArg o, TCGType low_type)
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{
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TCGArg ri = tcgv_vec_arg(r);
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TCGArg bi = tcgv_ptr_arg(b);
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TCGTemp *rt = arg_temp(ri);
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TCGType type = rt->base_type;
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tcg_debug_assert(low_type >= TCG_TYPE_V64);
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tcg_debug_assert(low_type <= type);
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vec_gen_3(INDEX_op_st_vec, low_type, 0, ri, bi, o);
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}
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void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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vec_gen_op3(INDEX_op_and_vec, 0, r, a, b);
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}
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void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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vec_gen_op3(INDEX_op_or_vec, 0, r, a, b);
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}
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void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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vec_gen_op3(INDEX_op_xor_vec, 0, r, a, b);
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}
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void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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if (TCG_TARGET_HAS_andc_vec) {
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vec_gen_op3(INDEX_op_andc_vec, 0, r, a, b);
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} else {
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TCGv_vec t = tcg_temp_new_vec_matching(r);
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tcg_gen_not_vec(0, t, b);
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tcg_gen_and_vec(0, r, a, t);
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tcg_temp_free_vec(t);
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}
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}
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void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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if (TCG_TARGET_HAS_orc_vec) {
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vec_gen_op3(INDEX_op_orc_vec, 0, r, a, b);
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} else {
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TCGv_vec t = tcg_temp_new_vec_matching(r);
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tcg_gen_not_vec(0, t, b);
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tcg_gen_or_vec(0, r, a, t);
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tcg_temp_free_vec(t);
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}
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}
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void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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/* TODO: Add TCG_TARGET_HAS_nand_vec when adding a backend supports it. */
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tcg_gen_and_vec(0, r, a, b);
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tcg_gen_not_vec(0, r, r);
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}
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void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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/* TODO: Add TCG_TARGET_HAS_nor_vec when adding a backend supports it. */
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tcg_gen_or_vec(0, r, a, b);
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tcg_gen_not_vec(0, r, r);
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}
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void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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/* TODO: Add TCG_TARGET_HAS_eqv_vec when adding a backend supports it. */
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tcg_gen_xor_vec(0, r, a, b);
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tcg_gen_not_vec(0, r, r);
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}
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static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc)
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{
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TCGTemp *rt = tcgv_vec_temp(r);
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TCGTemp *at = tcgv_vec_temp(a);
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TCGArg ri = temp_arg(rt);
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TCGArg ai = temp_arg(at);
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TCGType type = rt->base_type;
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int can;
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tcg_debug_assert(at->base_type >= type);
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tcg_assert_listed_vecop(opc);
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can = tcg_can_emit_vec_op(opc, type, vece);
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if (can > 0) {
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vec_gen_2(opc, type, vece, ri, ai);
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} else if (can < 0) {
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const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
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tcg_expand_vec_op(opc, type, vece, ri, ai);
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tcg_swap_vecop_list(hold_list);
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} else {
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return false;
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}
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return true;
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}
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void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
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{
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if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) {
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TCGv_vec t = tcg_const_ones_vec_matching(r);
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tcg_gen_xor_vec(0, r, a, t);
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tcg_temp_free_vec(t);
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}
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}
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void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
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{
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const TCGOpcode *hold_list;
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tcg_assert_listed_vecop(INDEX_op_neg_vec);
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hold_list = tcg_swap_vecop_list(NULL);
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if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) {
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TCGv_vec t = tcg_const_zeros_vec_matching(r);
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tcg_gen_sub_vec(vece, r, t, a);
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tcg_temp_free_vec(t);
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}
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tcg_swap_vecop_list(hold_list);
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}
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static void do_shifti(TCGOpcode opc, unsigned vece,
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TCGv_vec r, TCGv_vec a, int64_t i)
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{
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TCGTemp *rt = tcgv_vec_temp(r);
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TCGTemp *at = tcgv_vec_temp(a);
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TCGArg ri = temp_arg(rt);
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TCGArg ai = temp_arg(at);
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TCGType type = rt->base_type;
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int can;
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tcg_debug_assert(at->base_type == type);
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tcg_debug_assert(i >= 0 && i < (8 << vece));
|
|
tcg_assert_listed_vecop(opc);
|
|
|
|
if (i == 0) {
|
|
tcg_gen_mov_vec(r, a);
|
|
return;
|
|
}
|
|
|
|
can = tcg_can_emit_vec_op(opc, type, vece);
|
|
if (can > 0) {
|
|
vec_gen_3(opc, type, vece, ri, ai, i);
|
|
} else {
|
|
/* We leave the choice of expansion via scalar or vector shift
|
|
to the target. Often, but not always, dupi can feed a vector
|
|
shift easier than a scalar. */
|
|
const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
|
|
tcg_debug_assert(can < 0);
|
|
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
|
|
tcg_swap_vecop_list(hold_list);
|
|
}
|
|
}
|
|
|
|
void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
|
|
{
|
|
do_shifti(INDEX_op_shli_vec, vece, r, a, i);
|
|
}
|
|
|
|
void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
|
|
{
|
|
do_shifti(INDEX_op_shri_vec, vece, r, a, i);
|
|
}
|
|
|
|
void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
|
|
{
|
|
do_shifti(INDEX_op_sari_vec, vece, r, a, i);
|
|
}
|
|
|
|
void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
|
|
TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
TCGTemp *rt = tcgv_vec_temp(r);
|
|
TCGTemp *at = tcgv_vec_temp(a);
|
|
TCGTemp *bt = tcgv_vec_temp(b);
|
|
TCGArg ri = temp_arg(rt);
|
|
TCGArg ai = temp_arg(at);
|
|
TCGArg bi = temp_arg(bt);
|
|
TCGType type = rt->base_type;
|
|
int can;
|
|
|
|
tcg_debug_assert(at->base_type >= type);
|
|
tcg_debug_assert(bt->base_type >= type);
|
|
tcg_assert_listed_vecop(INDEX_op_cmp_vec);
|
|
can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
|
|
if (can > 0) {
|
|
vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
|
|
} else {
|
|
const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
|
|
tcg_debug_assert(can < 0);
|
|
tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
|
|
tcg_swap_vecop_list(hold_list);
|
|
}
|
|
}
|
|
|
|
static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec a,
|
|
TCGv_vec b, TCGOpcode opc)
|
|
{
|
|
TCGTemp *rt = tcgv_vec_temp(r);
|
|
TCGTemp *at = tcgv_vec_temp(a);
|
|
TCGTemp *bt = tcgv_vec_temp(b);
|
|
TCGArg ri = temp_arg(rt);
|
|
TCGArg ai = temp_arg(at);
|
|
TCGArg bi = temp_arg(bt);
|
|
TCGType type = rt->base_type;
|
|
int can;
|
|
|
|
tcg_debug_assert(at->base_type >= type);
|
|
tcg_debug_assert(bt->base_type >= type);
|
|
tcg_assert_listed_vecop(opc);
|
|
can = tcg_can_emit_vec_op(opc, type, vece);
|
|
if (can > 0) {
|
|
vec_gen_3(opc, type, vece, ri, ai, bi);
|
|
} else {
|
|
const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
|
|
tcg_debug_assert(can < 0);
|
|
tcg_expand_vec_op(opc, type, vece, ri, ai, bi);
|
|
tcg_swap_vecop_list(hold_list);
|
|
}
|
|
}
|
|
|
|
void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_add_vec);
|
|
}
|
|
|
|
void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_sub_vec);
|
|
}
|
|
|
|
void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_mul_vec);
|
|
}
|
|
|
|
void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_ssadd_vec);
|
|
}
|
|
|
|
void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_usadd_vec);
|
|
}
|
|
|
|
void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_sssub_vec);
|
|
}
|
|
|
|
void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_ussub_vec);
|
|
}
|
|
|
|
void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_smin_vec);
|
|
}
|
|
|
|
void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_umin_vec);
|
|
}
|
|
|
|
void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_smax_vec);
|
|
}
|
|
|
|
void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_umax_vec);
|
|
}
|
|
|
|
void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_shlv_vec);
|
|
}
|
|
|
|
void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_shrv_vec);
|
|
}
|
|
|
|
void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|
{
|
|
do_op3(vece, r, a, b, INDEX_op_sarv_vec);
|
|
}
|
|
|
|
static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,
|
|
TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v)
|
|
{
|
|
TCGTemp *rt = tcgv_vec_temp(r);
|
|
TCGTemp *at = tcgv_vec_temp(a);
|
|
TCGTemp *st = tcgv_i32_temp(s);
|
|
TCGArg ri = temp_arg(rt);
|
|
TCGArg ai = temp_arg(at);
|
|
TCGArg si = temp_arg(st);
|
|
TCGType type = rt->base_type;
|
|
const TCGOpcode *hold_list;
|
|
int can;
|
|
|
|
tcg_debug_assert(at->base_type >= type);
|
|
tcg_assert_listed_vecop(opc_s);
|
|
hold_list = tcg_swap_vecop_list(NULL);
|
|
|
|
can = tcg_can_emit_vec_op(opc_s, type, vece);
|
|
if (can > 0) {
|
|
vec_gen_3(opc_s, type, vece, ri, ai, si);
|
|
} else if (can < 0) {
|
|
tcg_expand_vec_op(opc_s, type, vece, ri, ai, si);
|
|
} else {
|
|
TCGv_vec vec_s = tcg_temp_new_vec(type);
|
|
|
|
if (vece == MO_64) {
|
|
TCGv_i64 s64 = tcg_temp_new_i64();
|
|
tcg_gen_extu_i32_i64(s64, s);
|
|
tcg_gen_dup_i64_vec(MO_64, vec_s, s64);
|
|
tcg_temp_free_i64(s64);
|
|
} else {
|
|
tcg_gen_dup_i32_vec(vece, vec_s, s);
|
|
}
|
|
do_op3(vece, r, a, vec_s, opc_v);
|
|
tcg_temp_free_vec(vec_s);
|
|
}
|
|
tcg_swap_vecop_list(hold_list);
|
|
}
|
|
|
|
void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
|
|
{
|
|
do_shifts(vece, r, a, b, INDEX_op_shls_vec, INDEX_op_shlv_vec);
|
|
}
|
|
|
|
void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
|
|
{
|
|
do_shifts(vece, r, a, b, INDEX_op_shrs_vec, INDEX_op_shrv_vec);
|
|
}
|
|
|
|
void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
|
|
{
|
|
do_shifts(vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec);
|
|
}
|