Laurent Vivier b6a21d8d8f target/m68k: add 680x0 "move to SR" instruction ... Some cleanup, and allows SR to be moved from any addressing mode. Previous code was wrong for coldfire: coldfire also allows to use addressing mode to set SR/CCR. It only supports Data register to get SR/CCR (move from) Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-15-laurent@vivier.eu>		2018-01-04 17:24:35 +01:00
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alpha	x86/cpu/numa queue, 2017-10-27	2017-10-30 10:11:22 +00:00
arm	cpu: refactor cpu_address_space_init()	2017-12-21 09:30:31 +01:00
cris	x86/cpu/numa queue, 2017-10-27	2017-10-30 10:11:22 +00:00
hppa	Capstone disassembler	2017-10-27 08:04:51 +01:00
i386	cpu: refactor cpu_address_space_init()	2017-12-21 09:30:31 +01:00
lm32	x86/cpu/numa queue, 2017-10-27	2017-10-30 10:11:22 +00:00
m68k	target/m68k: add 680x0 "move to SR" instruction	2018-01-04 17:24:35 +01:00
microblaze	Capstone disassembler	2017-10-27 08:04:51 +01:00
mips	x86/cpu/numa queue, 2017-10-27	2017-10-30 10:11:22 +00:00
moxie	moxie: cleanup cpu type name composition	2017-10-27 16:03:54 +02:00
nios2	nios2: remove duplicated includes (in code commented out)	2017-12-18 17:07:02 +03:00
openrisc	misc: remove duplicated includes	2017-12-18 17:07:02 +03:00
ppc	ppc: remove duplicated includes	2017-12-18 17:07:02 +03:00
s390x	s390x: change the QEMU cpu model to a stripped down z12	2017-12-14 17:56:54 +01:00
sh4	target/sh4: Convert to DisasContextBase	2017-12-18 23:35:33 +01:00
sparc	linux-user/sparc: Put address for data faults where linux-user expects it	2017-11-07 21:59:18 +02:00
tilegx	tcg: Initialize cpu_env generically	2017-10-24 13:53:42 -07:00
tricore	x86/cpu/numa queue, 2017-10-27	2017-10-30 10:11:22 +00:00
unicore32	x86/cpu/numa queue, 2017-10-27	2017-10-30 10:11:22 +00:00
xtensa	x86/cpu/numa queue, 2017-10-27	2017-10-30 10:11:22 +00:00