xemu/accel
Peter Maydell f454a54f3b accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
In cpu_signal_handler() for aarch64 hosts, currently we parse
the faulting instruction to see if it is a load or a store.
Since the 3.16 kernel (~2014), the kernel has provided us with
the syndrome register for a fault, which includes the WnR bit.
Use this instead if it is present, only falling back to
instruction parsing if not.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190108180014.32386-1-peter.maydell@linaro.org
2019-01-29 11:46:04 +00:00
..
kvm qemu/queue.h: leave head structs anonymous unless necessary 2019-01-11 15:46:55 +01:00
stubs tcg: simplify !CONFIG_TCG handling of tb_invalidate_* 2018-07-02 15:41:18 +02:00
tcg accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write 2019-01-29 11:46:04 +00:00
accel.c accel: Improve selection of the default accelerator 2019-01-11 13:57:23 +01:00
Makefile.objs kvm: add memory encryption context 2018-03-13 12:04:03 +01:00