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c11a8e890c
Currently the documentation for Arm system emulator targets is in a
single target-arm.rst. This describes only some of the boards and
often in a fairly abbreviated fashion. Restructure it so that each
board has its own documentation file in the docs/system/arm/
subdirectory.
This will hopefully encourage us to write board documentation that
describes the board in detail, rather than a few brief paragraphs
in a single long page. The table of contents should also help users
to find the board they care about faster.
Once the structure is in place we'll be able to move microvm.rst
from the top-level docs/ directory.
All the text from the old page is retained, except for the final
paragraph ("A Linux 2.6 test image is available on the QEMU web site.
More information is available in the QEMU mailing-list archive."),
which is deleted. The git history shows this was originally added
in reference to the integratorcp board (at that time the only
Arm board that was supported), and has subsequently gradually been
further and further separated from the integratorcp documentation
by the insertion of other board documentation sections. It's
extremely out of date and no longer accurate, since AFAICT there
isn't an integratorcp kernel on the website any more; so better
deleted than retained.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20200309215818.2021-3-peter.maydell@linaro.org
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Stellaris boards (``lm3s6965evb``, ``lm3s811evb``)
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The Luminary Micro Stellaris LM3S811EVB emulation includes the following
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devices:
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- Cortex-M3 CPU core.
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- 64k Flash and 8k SRAM.
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- Timers, UARTs, ADC and |I2C| interface.
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- OSRAM Pictiva 96x16 OLED with SSD0303 controller on
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|I2C| bus.
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The Luminary Micro Stellaris LM3S6965EVB emulation includes the
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following devices:
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- Cortex-M3 CPU core.
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- 256k Flash and 64k SRAM.
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- Timers, UARTs, ADC, |I2C| and SSI interfaces.
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- OSRAM Pictiva 128x64 OLED with SSD0323 controller connected via
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SSI.
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