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32d98fbd10
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
72 lines
2.3 KiB
C
72 lines
2.3 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define TCG_TARGET_I386 1
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#define TCG_TARGET_REG_BITS 32
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//#define TCG_TARGET_WORDS_BIGENDIAN
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#define TCG_TARGET_NB_REGS 8
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enum {
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TCG_REG_EAX = 0,
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TCG_REG_ECX,
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TCG_REG_EDX,
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TCG_REG_EBX,
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TCG_REG_ESP,
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TCG_REG_EBP,
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TCG_REG_ESI,
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TCG_REG_EDI,
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};
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_ESP
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#define TCG_TARGET_STACK_ALIGN 16
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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/* optional instructions */
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#define TCG_TARGET_HAS_div2_i32
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#define TCG_TARGET_HAS_rot_i32
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#define TCG_TARGET_HAS_ext8s_i32
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#define TCG_TARGET_HAS_ext16s_i32
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#define TCG_TARGET_HAS_ext8u_i32
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#define TCG_TARGET_HAS_ext16u_i32
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#define TCG_TARGET_HAS_bswap16_i32
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#define TCG_TARGET_HAS_bswap32_i32
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#define TCG_TARGET_HAS_neg_i32
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#define TCG_TARGET_HAS_not_i32
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// #define TCG_TARGET_HAS_andc_i32
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// #define TCG_TARGET_HAS_orc_i32
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// #define TCG_TARGET_HAS_eqv_i32
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// #define TCG_TARGET_HAS_nand_i32
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// #define TCG_TARGET_HAS_nor_i32
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#define TCG_TARGET_HAS_GUEST_BASE
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/* Note: must be synced with dyngen-exec.h */
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#define TCG_AREG0 TCG_REG_EBP
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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