Max Filippov 10df8ff146 target/xtensa: add MX interrupt controller ...

MX interrupt controller is a collection of the following devices
accessible through the external registers interface:
- interrupt distributor can route each external IRQ line to the
  corresponding external IRQ pin of selected subset of connected xtensa
  cores. It has per-CPU and per-IRQ enable signals and per-IRQ software
  assert signals;
- IPI controller has 16 per-CPU IPI signals that may be routed to a
  combination of 3 designated external IRQ pins of connected xtensa
  cores;
- cache coherecy register controls core L1 cache participation in the
  SMP cluster cache coherency protocol;
- runstall register lets BSP core stall and unstall AP cores.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

2019-01-28 11:55:20 -08:00

..

mx_pic.h

target/xtensa: add MX interrupt controller

2019-01-28 11:55:20 -08:00

xtensa-isa.h

Clean up includes

2018-02-09 05:05:11 +01:00