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xemu/hw/pci-bridge
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Jonathan Cameron 0b4aec2469 CXL/cxl_component: Add cxl_get_hb_cstate() 
Accessor to get hold of the cxl state for a CXL host bridge
without exposing the internals of the implementation.

Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-32-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-05-13 07:57:26 -04:00
..
cxl_root_port.c hw/cxl/rp: Add a root port 2022-05-13 06:13:36 -04:00
dec.c Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
dec.h Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
gen_pcie_root_port.c hw/pcie-root-port: Fix hotplug for PCI devices requiring IO 2021-08-03 16:31:07 -04:00
i82801b11.c nomaintainer: Fix Lesser GPL version number 2020-11-15 17:04:40 +01:00
ioh3420.c Include migration/vmstate.h less 2019-08-16 13:31:52 +02:00
Kconfig hw/cxl/rp: Add a root port 2022-05-13 06:13:36 -04:00
meson.build hw/cxl/rp: Add a root port 2022-05-13 06:13:36 -04:00
pci_bridge_dev.c Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
pci_expander_bridge.c CXL/cxl_component: Add cxl_get_hb_cstate() 2022-05-13 07:57:26 -04:00
pcie_pci_bridge.c Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
pcie_root_port.c hw/cxl/rp: Add a root port 2022-05-13 06:13:36 -04:00
simba.c Include qemu/module.h where needed, drop it from qemu-common.h 2019-06-12 13:18:33 +02:00
xio3130_downstream.c pci: expose TYPE_XIO3130_DOWNSTREAM name 2022-03-06 05:08:23 -05:00
xio3130_upstream.c pci-bridge/xio3130_upstream: Fix error handling 2022-03-06 05:08:23 -05:00