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c527e0afcd
Since commit ab06ec4357 we test the vmxnet3 device in the
pxe-tester, too (when running "make check SPEED=slow"). This now
revealed that the code is not working there if the host is a big
endian machine (for example ppc64 or s390x) - "make check SPEED=slow"
is now failing on such hosts.
The vmxnet3 code lacks endianness conversions in a couple of places.
Interestingly, the bitfields in the structs in vmxnet3.h already tried to
take care of the *bit* endianness of the C compilers - but the code missed
to change the *byte* endianness when reading or writing the corresponding
structs. So the bitfields are now wrapped into unions which allow to change
the byte endianness during runtime with the non-bitfield member of the union.
With these changes, "make check SPEED=slow" now properly works on big endian
hosts, too.
Reported-by: David Gibson <dgibson@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: David Gibson <dgibson@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
154 lines
3.9 KiB
C
154 lines
3.9 KiB
C
/*
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* QEMU VMWARE paravirtual devices - auxiliary code
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*
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* Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
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*
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* Developed by Daynix Computing LTD (http://www.daynix.com)
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*
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* Authors:
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* Dmitry Fleytman <dmitry@daynix.com>
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* Yan Vugenfirer <yan@daynix.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef VMWARE_UTILS_H
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#define VMWARE_UTILS_H
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#include "qemu/range.h"
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#include "vmxnet_debug.h"
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/*
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* Shared memory access functions with byte swap support
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* Each function contains printout for reverse-engineering needs
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*
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*/
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static inline void
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vmw_shmem_read(PCIDevice *d, hwaddr addr, void *buf, int len)
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{
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VMW_SHPRN("SHMEM r: %" PRIx64 ", len: %d to %p", addr, len, buf);
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pci_dma_read(d, addr, buf, len);
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}
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static inline void
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vmw_shmem_write(PCIDevice *d, hwaddr addr, void *buf, int len)
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{
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VMW_SHPRN("SHMEM w: %" PRIx64 ", len: %d to %p", addr, len, buf);
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pci_dma_write(d, addr, buf, len);
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}
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static inline void
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vmw_shmem_rw(PCIDevice *d, hwaddr addr, void *buf, int len, int is_write)
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{
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VMW_SHPRN("SHMEM r/w: %" PRIx64 ", len: %d (to %p), is write: %d",
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addr, len, buf, is_write);
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if (is_write)
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pci_dma_write(d, addr, buf, len);
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else
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pci_dma_read(d, addr, buf, len);
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}
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static inline void
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vmw_shmem_set(PCIDevice *d, hwaddr addr, uint8_t val, int len)
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{
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int i;
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VMW_SHPRN("SHMEM set: %" PRIx64 ", len: %d (value 0x%X)", addr, len, val);
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for (i = 0; i < len; i++) {
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pci_dma_write(d, addr + i, &val, 1);
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}
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}
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static inline uint32_t
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vmw_shmem_ld8(PCIDevice *d, hwaddr addr)
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{
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uint8_t res;
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pci_dma_read(d, addr, &res, 1);
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VMW_SHPRN("SHMEM load8: %" PRIx64 " (value 0x%X)", addr, res);
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return res;
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}
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static inline void
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vmw_shmem_st8(PCIDevice *d, hwaddr addr, uint8_t value)
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{
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VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value);
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pci_dma_write(d, addr, &value, 1);
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}
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static inline uint32_t
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vmw_shmem_ld16(PCIDevice *d, hwaddr addr)
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{
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uint16_t res;
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pci_dma_read(d, addr, &res, 2);
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res = le16_to_cpu(res);
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VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res);
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return res;
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}
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static inline void
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vmw_shmem_st16(PCIDevice *d, hwaddr addr, uint16_t value)
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{
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VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value);
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value = cpu_to_le16(value);
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pci_dma_write(d, addr, &value, 2);
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}
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static inline uint32_t
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vmw_shmem_ld32(PCIDevice *d, hwaddr addr)
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{
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uint32_t res;
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pci_dma_read(d, addr, &res, 4);
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res = le32_to_cpu(res);
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VMW_SHPRN("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res);
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return res;
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}
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static inline void
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vmw_shmem_st32(PCIDevice *d, hwaddr addr, uint32_t value)
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{
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VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value);
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value = cpu_to_le32(value);
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pci_dma_write(d, addr, &value, 4);
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}
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static inline uint64_t
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vmw_shmem_ld64(PCIDevice *d, hwaddr addr)
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{
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uint64_t res;
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pci_dma_read(d, addr, &res, 8);
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res = le64_to_cpu(res);
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VMW_SHPRN("SHMEM load64: %" PRIx64 " (value %" PRIx64 ")", addr, res);
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return res;
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}
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static inline void
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vmw_shmem_st64(PCIDevice *d, hwaddr addr, uint64_t value)
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{
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VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value);
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value = cpu_to_le64(value);
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pci_dma_write(d, addr, &value, 8);
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}
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/* Macros for simplification of operations on array-style registers */
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/*
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* Whether <addr> lies inside of array-style register defined by <base>,
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* number of elements (<cnt>) and element size (<regsize>)
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*
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*/
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#define VMW_IS_MULTIREG_ADDR(addr, base, cnt, regsize) \
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range_covers_byte(base, cnt * regsize, addr)
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/*
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* Returns index of given register (<addr>) in array-style register defined by
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* <base> and element size (<regsize>)
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*
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*/
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#define VMW_MULTIREG_IDX_BY_ADDR(addr, base, regsize) \
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(((addr) - (base)) / (regsize))
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#endif
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