Wilfred Mallawa bf8803c64d hw/riscv: opentitan: bump opentitan version ...

The following patch updates opentitan to match the new configuration,
as per, lowRISC/opentitan@217a0168ba

Note: with this patch we now skip the usage of the opentitan
`boot_rom`. The Opentitan boot rom contains hw verification
for devies which we are currently not supporting in qemu. As of now,
the `boot_rom` has no major significance, however, would be good to
support in the future.

Tested by running utests from the latest tock [1]
(that supports this version of OT).

[1] https://github.com/tock/tock/pull/3056

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220812005229.358850-1-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2022-09-07 09:18:33 +02:00

..

boot.c

hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

2022-09-07 09:18:33 +02:00

Kconfig

hw/riscv: Enable TPM backends

2022-04-29 10:48:48 +10:00

meson.build

hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines

2021-07-20 15:32:49 +02:00

microchip_pfsoc.c

hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

2022-09-07 09:18:33 +02:00

numa.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

opentitan.c

hw/riscv: opentitan: bump opentitan version

2022-09-07 09:18:33 +02:00

riscv_hart.c

hw/riscv: hart: Add a new 'resetvec' property

2020-09-09 15:54:18 -07:00

shakti_c.c

hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

2022-09-07 09:18:33 +02:00

sifive_e.c

hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)

2022-05-24 10:38:50 +10:00

sifive_u.c

hw/riscv/sifive_u: Resolve redundant property accessors

2022-05-24 10:38:50 +10:00

spike.c

hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

2022-09-07 09:18:33 +02:00

virt.c

hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

2022-09-07 09:18:33 +02:00