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c165473269
We set default boot order "cad" in every single machine definition except "pseries" and "moxiesim", even though very few boards actually care for boot order, and "cad" makes sense for even fewer. Machines that care: * pc and its variants Accept up to three letters 'a', 'b' (undocumented alias for 'a'), 'c', 'd' and 'n'. Reject all others (fatal with -boot). * nseries (n800, n810) Check whether order starts with 'n'. Silently ignored otherwise. * prep, g3beige, mac99 Extract the first character the machine understands (subset of 'a'..'f'). Silently ignored otherwise. * spapr Accept an arbitrary string (vl.c restricts it to contain only 'a'..'p', no duplicates). * sun4[mdc] Use the first character. Silently ignored otherwise. Strip characters these machines ignore from their default boot order. For all other machines, remove the unused default boot order alltogether. Note that my rename of QEMUMachine member boot_order to default_boot_order and QEMUMachineInitArgs member boot_device to boot_order has a welcome side effect: it makes every use of boot orders visible in this patch, for easy review. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
308 lines
9.9 KiB
C
308 lines
9.9 KiB
C
/*
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* QEMU models for LatticeMico32 uclinux and evr32 boards.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/sysbus.h"
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#include "hw/hw.h"
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#include "hw/block/flash.h"
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#include "hw/devices.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "sysemu/blockdev.h"
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#include "elf.h"
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#include "lm32_hwsetup.h"
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#include "lm32.h"
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#include "exec/address-spaces.h"
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typedef struct {
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LM32CPU *cpu;
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hwaddr bootstrap_pc;
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hwaddr flash_base;
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hwaddr hwsetup_base;
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hwaddr initrd_base;
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size_t initrd_size;
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hwaddr cmdline_base;
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} ResetInfo;
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static void cpu_irq_handler(void *opaque, int irq, int level)
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{
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LM32CPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static void main_cpu_reset(void *opaque)
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{
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ResetInfo *reset_info = opaque;
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CPULM32State *env = &reset_info->cpu->env;
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cpu_reset(CPU(reset_info->cpu));
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/* init defaults */
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env->pc = (uint32_t)reset_info->bootstrap_pc;
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env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
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env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
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env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
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env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
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reset_info->initrd_size);
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env->eba = reset_info->flash_base;
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env->deba = reset_info->flash_base;
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}
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static void lm32_evr_init(QEMUMachineInitArgs *args)
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{
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const char *cpu_model = args->cpu_model;
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const char *kernel_filename = args->kernel_filename;
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LM32CPU *cpu;
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CPULM32State *env;
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DriveInfo *dinfo;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
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qemu_irq *cpu_irq, irq[32];
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ResetInfo *reset_info;
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int i;
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/* memory map */
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hwaddr flash_base = 0x04000000;
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size_t flash_sector_size = 256 * 1024;
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size_t flash_size = 32 * 1024 * 1024;
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hwaddr ram_base = 0x08000000;
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size_t ram_size = 64 * 1024 * 1024;
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hwaddr timer0_base = 0x80002000;
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hwaddr uart0_base = 0x80006000;
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hwaddr timer1_base = 0x8000a000;
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int uart0_irq = 0;
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int timer0_irq = 1;
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int timer1_irq = 3;
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reset_info = g_malloc0(sizeof(ResetInfo));
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if (cpu_model == NULL) {
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cpu_model = "lm32-full";
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}
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cpu = cpu_lm32_init(cpu_model);
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env = &cpu->env;
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reset_info->cpu = cpu;
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reset_info->flash_base = flash_base;
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memory_region_init_ram(phys_ram, NULL, "lm32_evr.sdram", ram_size);
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vmstate_register_ram_global(phys_ram);
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memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
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dinfo = drive_get(IF_PFLASH, 0, 0);
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/* Spansion S29NS128P */
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pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
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dinfo ? dinfo->bdrv : NULL, flash_sector_size,
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flash_size / flash_sector_size, 1, 2,
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0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
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/* create irq lines */
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cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
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env->pic_state = lm32_pic_init(*cpu_irq);
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for (i = 0; i < 32; i++) {
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irq[i] = qdev_get_gpio_in(env->pic_state, i);
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}
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sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
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sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
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sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
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/* make sure juart isn't the first chardev */
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env->juart_state = lm32_juart_init();
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reset_info->bootstrap_pc = flash_base;
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if (kernel_filename) {
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uint64_t entry;
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int kernel_size;
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kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
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1, ELF_MACHINE, 0);
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reset_info->bootstrap_pc = entry;
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if (kernel_size < 0) {
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kernel_size = load_image_targphys(kernel_filename, ram_base,
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ram_size);
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reset_info->bootstrap_pc = ram_base;
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}
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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}
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qemu_register_reset(main_cpu_reset, reset_info);
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}
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static void lm32_uclinux_init(QEMUMachineInitArgs *args)
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{
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const char *cpu_model = args->cpu_model;
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const char *kernel_filename = args->kernel_filename;
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const char *kernel_cmdline = args->kernel_cmdline;
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const char *initrd_filename = args->initrd_filename;
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LM32CPU *cpu;
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CPULM32State *env;
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DriveInfo *dinfo;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
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qemu_irq *cpu_irq, irq[32];
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HWSetup *hw;
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ResetInfo *reset_info;
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int i;
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/* memory map */
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hwaddr flash_base = 0x04000000;
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size_t flash_sector_size = 256 * 1024;
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size_t flash_size = 32 * 1024 * 1024;
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hwaddr ram_base = 0x08000000;
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size_t ram_size = 64 * 1024 * 1024;
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hwaddr uart0_base = 0x80000000;
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hwaddr timer0_base = 0x80002000;
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hwaddr timer1_base = 0x80010000;
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hwaddr timer2_base = 0x80012000;
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int uart0_irq = 0;
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int timer0_irq = 1;
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int timer1_irq = 20;
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int timer2_irq = 21;
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hwaddr hwsetup_base = 0x0bffe000;
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hwaddr cmdline_base = 0x0bfff000;
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hwaddr initrd_base = 0x08400000;
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size_t initrd_max = 0x01000000;
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reset_info = g_malloc0(sizeof(ResetInfo));
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if (cpu_model == NULL) {
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cpu_model = "lm32-full";
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}
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cpu = cpu_lm32_init(cpu_model);
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env = &cpu->env;
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reset_info->cpu = cpu;
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reset_info->flash_base = flash_base;
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memory_region_init_ram(phys_ram, NULL, "lm32_uclinux.sdram", ram_size);
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vmstate_register_ram_global(phys_ram);
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memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
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dinfo = drive_get(IF_PFLASH, 0, 0);
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/* Spansion S29NS128P */
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pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
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dinfo ? dinfo->bdrv : NULL, flash_sector_size,
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flash_size / flash_sector_size, 1, 2,
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0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
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/* create irq lines */
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cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
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env->pic_state = lm32_pic_init(*cpu_irq);
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for (i = 0; i < 32; i++) {
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irq[i] = qdev_get_gpio_in(env->pic_state, i);
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}
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sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
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sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
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sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
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sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
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/* make sure juart isn't the first chardev */
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env->juart_state = lm32_juart_init();
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reset_info->bootstrap_pc = flash_base;
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if (kernel_filename) {
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uint64_t entry;
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int kernel_size;
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kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
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1, ELF_MACHINE, 0);
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reset_info->bootstrap_pc = entry;
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if (kernel_size < 0) {
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kernel_size = load_image_targphys(kernel_filename, ram_base,
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ram_size);
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reset_info->bootstrap_pc = ram_base;
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}
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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}
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/* generate a rom with the hardware description */
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hw = hwsetup_init();
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hwsetup_add_cpu(hw, "LM32", 75000000);
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hwsetup_add_flash(hw, "flash", flash_base, flash_size);
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hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
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hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
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hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
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hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
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hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
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hwsetup_add_trailer(hw);
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hwsetup_create_rom(hw, hwsetup_base);
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hwsetup_free(hw);
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reset_info->hwsetup_base = hwsetup_base;
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if (kernel_cmdline && strlen(kernel_cmdline)) {
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pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
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kernel_cmdline);
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reset_info->cmdline_base = cmdline_base;
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}
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if (initrd_filename) {
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size_t initrd_size;
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initrd_size = load_image_targphys(initrd_filename, initrd_base,
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initrd_max);
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reset_info->initrd_base = initrd_base;
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reset_info->initrd_size = initrd_size;
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}
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qemu_register_reset(main_cpu_reset, reset_info);
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}
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static QEMUMachine lm32_evr_machine = {
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.name = "lm32-evr",
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.desc = "LatticeMico32 EVR32 eval system",
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.init = lm32_evr_init,
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.is_default = 1,
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};
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static QEMUMachine lm32_uclinux_machine = {
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.name = "lm32-uclinux",
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.desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
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.init = lm32_uclinux_init,
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.is_default = 0,
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};
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static void lm32_machine_init(void)
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{
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qemu_register_machine(&lm32_uclinux_machine);
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qemu_register_machine(&lm32_evr_machine);
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}
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machine_init(lm32_machine_init);
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