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The SSE-300 has a new register block CPU<N>_PWRCTRL. There is one instance of this per CPU in the system (so just one for the SSE-300), and as well as the usual CIDR/PIDR ID registers it has just one register, CPUPWRCFG. This register allows the guest to configure behaviour of the system in power-down and deep-sleep states. Since QEMU does not model those, we make the register a dummy reads-as-written implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-21-peter.maydell@linaro.org
150 lines
3.7 KiB
C
150 lines
3.7 KiB
C
/*
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* Arm SSE CPU PWRCTRL register block
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*
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* Copyright (c) 2021 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "CPU<N>_PWRCTRL block" which is part of the
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* Arm Corstone SSE-300 Example Subsystem and documented in
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* https://developer.arm.com/documentation/101773/0000
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/misc/armsse-cpu-pwrctrl.h"
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REG32(CPUPWRCFG, 0x0)
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REG32(PID4, 0xfd0)
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REG32(PID5, 0xfd4)
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REG32(PID6, 0xfd8)
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REG32(PID7, 0xfdc)
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REG32(PID0, 0xfe0)
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REG32(PID1, 0xfe4)
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REG32(PID2, 0xfe8)
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REG32(PID3, 0xfec)
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REG32(CID0, 0xff0)
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REG32(CID1, 0xff4)
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REG32(CID2, 0xff8)
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REG32(CID3, 0xffc)
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/* PID/CID values */
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static const int cpu_pwrctrl_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0x5a, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static uint64_t pwrctrl_read(void *opaque, hwaddr offset, unsigned size)
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{
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ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(opaque);
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uint64_t r;
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switch (offset) {
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case A_CPUPWRCFG:
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r = s->cpupwrcfg;
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break;
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case A_PID4 ... A_CID3:
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r = cpu_pwrctrl_id[(offset - A_PID4) / 4];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE CPU_PWRCTRL read: bad offset %x\n", (int)offset);
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r = 0;
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break;
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}
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trace_armsse_cpu_pwrctrl_read(offset, r, size);
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return r;
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}
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static void pwrctrl_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(opaque);
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trace_armsse_cpu_pwrctrl_write(offset, value, size);
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switch (offset) {
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case A_CPUPWRCFG:
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qemu_log_mask(LOG_UNIMP,
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"SSE CPU_PWRCTRL: CPUPWRCFG unimplemented\n");
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s->cpupwrcfg = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SSE CPU_PWRCTRL write: bad offset 0x%x\n", (int)offset);
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break;
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}
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}
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static const MemoryRegionOps pwrctrl_ops = {
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.read = pwrctrl_read,
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.write = pwrctrl_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void pwrctrl_reset(DeviceState *dev)
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{
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ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(dev);
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s->cpupwrcfg = 0;
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}
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static const VMStateDescription pwrctrl_vmstate = {
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.name = "armsse-cpu-pwrctrl",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cpupwrcfg, ARMSSECPUPwrCtrl),
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VMSTATE_END_OF_LIST()
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},
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};
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static void pwrctrl_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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ARMSSECPUPwrCtrl *s = ARMSSE_CPU_PWRCTRL(obj);
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memory_region_init_io(&s->iomem, obj, &pwrctrl_ops,
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s, "armsse-cpu-pwrctrl", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void pwrctrl_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = pwrctrl_reset;
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dc->vmsd = &pwrctrl_vmstate;
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}
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static const TypeInfo pwrctrl_info = {
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.name = TYPE_ARMSSE_CPU_PWRCTRL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARMSSECPUPwrCtrl),
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.instance_init = pwrctrl_init,
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.class_init = pwrctrl_class_init,
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};
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static void pwrctrl_register_types(void)
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{
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type_register_static(&pwrctrl_info);
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}
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type_init(pwrctrl_register_types);
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