Jonathan Cameron 18cef1c6a5 pci-bridge/cxl_downstream: Add a CXL switch downstream port ... Emulation of a simple CXL Switch downstream port. The Device ID has been allocated for this use. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20220616145126.8002-3-Jonathan.Cameron@huawei.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2022-06-16 12:54:57 -04:00
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cxl-component-utils.c	hw/cxl: Fix missing write mask for HDM decoder target list registers	2022-06-09 19:32:49 -04:00
cxl-device-utils.c	hw/cxl/device: Add memory device utilities	2022-05-13 06:13:36 -04:00
cxl-host-stubs.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
cxl-host.c	pci-bridge/cxl_downstream: Add a CXL switch downstream port	2022-06-16 12:54:57 -04:00
cxl-mailbox-utils.c	hw/cxl/device: Implement get/set Label Storage Area (LSA)	2022-05-13 06:13:36 -04:00
Kconfig	hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)	2022-05-13 06:13:35 -04:00
meson.build	hw/cxl/host: Add support for CXL Fixed Memory Windows.	2022-05-13 07:57:26 -04:00