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f7c4acf572
Now we've converted all the callsites to directly create the QOM UIC device themselves, the ppcuic_init() function is unused and can be removed. The enum defining PPCUIC symbolic constants can be moved to the ppc-uic.h header where it more naturally belongs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20210108171212.16500-5-peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
81 lines
2.6 KiB
C
81 lines
2.6 KiB
C
/*
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* "Universal" Interrupt Controller for PowerPPC 4xx embedded processors
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_INTC_PPC_UIC_H
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#define HW_INTC_PPC_UIC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_PPC_UIC "ppc-uic"
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OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC)
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/*
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* QEMU interface:
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* QOM property "cpu": link to the PPC CPU
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* (no default, must be set)
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* QOM property "dcr-base": base of the bank of DCR registers for the UIC
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* (default 0x30)
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* QOM property "use-vectors": true if the UIC has vector registers
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* (default true)
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* unnamed GPIO inputs 0..UIC_MAX_IRQ: input IRQ lines
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* sysbus IRQs:
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* 0 (PPCUIC_OUTPUT_INT): output INT line to the CPU
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* 1 (PPCUIC_OUTPUT_CINT): output CINT line to the CPU
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*/
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#define UIC_MAX_IRQ 32
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/* Symbolic constants for the sysbus IRQ outputs */
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enum {
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PPCUIC_OUTPUT_INT = 0,
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PPCUIC_OUTPUT_CINT = 1,
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PPCUIC_OUTPUT_NB,
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};
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struct PPCUIC {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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qemu_irq output_int;
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qemu_irq output_cint;
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/* properties */
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CPUState *cpu;
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uint32_t dcr_base;
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bool use_vectors;
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uint32_t level; /* Remembers the state of level-triggered interrupts. */
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uint32_t uicsr; /* Status register */
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uint32_t uicer; /* Enable register */
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uint32_t uiccr; /* Critical register */
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uint32_t uicpr; /* Polarity register */
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uint32_t uictr; /* Triggering register */
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uint32_t uicvcr; /* Vector configuration register */
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uint32_t uicvr;
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};
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#endif
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