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qemu-barrier.h contains a few macros implementing memory barrier primitives used in several places throughout qemu. However, apart from the compiler-only barrier, the defined wmb() is correct only for x86, or platforms which are similarly strongly ordered. This patch addresses the FIXME about this by making the wmb() macro arch dependent. On x86, it remains a compiler barrier only, but with a comment explaining in more detail the conditions under which this is correct. On weakly-ordered powerpc, an "eieio" instruction is used, again with explanation of the conditions under which it is sufficient. On other platforms, we use the __sync_synchronize() primitive, available in sufficiently recent gcc (4.2 and after?). This should implement a full barrier which will be sufficient on all platforms, although it may be overkill in some cases. Other platforms can add optimized versions in future if it's worth it for them. Without proper memory barriers, it is easy to reproduce ordering problems with virtio on powerpc; specifically, the QEMU puts new element into the "used" ring and then updates the ring free-running counter. Without a barrier between these under the right circumstances, the guest linux driver can receive an interrupt, read the counter change but find the ring element to be handled still has an old value, leading to an "id %u is not a head!\n" error message. Similar problems are likely to be possible with kvm on other weakly ordered platforms. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
39 lines
980 B
C
39 lines
980 B
C
#ifndef __QEMU_BARRIER_H
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#define __QEMU_BARRIER_H 1
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/* Compiler barrier */
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#define barrier() asm volatile("" ::: "memory")
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#if defined(__i386__) || defined(__x86_64__)
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/*
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* Because of the strongly ordered x86 storage model, wmb() is a nop
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* on x86(well, a compiler barrier only). Well, at least as long as
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* qemu doesn't do accesses to write-combining memory or non-temporal
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* load/stores from C code.
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*/
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#define smp_wmb() barrier()
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#elif defined(__powerpc__)
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/*
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* We use an eieio() for a wmb() on powerpc. This assumes we don't
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* need to order cacheable and non-cacheable stores with respect to
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* each other
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*/
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#define smp_wmb() asm volatile("eieio" ::: "memory")
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#else
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/*
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* For (host) platforms we don't have explicit barrier definitions
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* for, we use the gcc __sync_synchronize() primitive to generate a
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* full barrier. This should be safe on all platforms, though it may
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* be overkill.
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*/
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#define smp_wmb() __sync_synchronize()
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#endif
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#endif
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