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d89e71e873
Shadow registers are part of the openrisc spec along with sr[cid], as part of the fast context switching feature. When exceptions occur, instead of having to save registers to the stack if enabled the CID will increment and a new set of registers will be available. This patch only implements shadow registers which can be used as extra scratch registers via the mfspr and mtspr if required. This is implemented in a way where it would be easy to add on the fast context switching, currently cid is hardcoded to 0. This is need for openrisc linux smp kernels to boot correctly. Signed-off-by: Stafford Horne <shorne@gmail.com>
28 lines
582 B
C
28 lines
582 B
C
#ifndef OPENRISC_TARGET_SIGNAL_H
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#define OPENRISC_TARGET_SIGNAL_H
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#include "cpu.h"
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/* this struct defines a stack used during syscall handling */
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typedef struct target_sigaltstack {
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abi_long ss_sp;
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abi_ulong ss_size;
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abi_long ss_flags;
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} target_stack_t;
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/* sigaltstack controls */
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#define TARGET_SS_ONSTACK 1
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#define TARGET_SS_DISABLE 2
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#define TARGET_MINSIGSTKSZ 2048
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#define TARGET_SIGSTKSZ 8192
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static inline abi_ulong get_sp_from_cpustate(CPUOpenRISCState *state)
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{
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return cpu_get_gpr(state, 1);
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}
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#endif /* OPENRISC_TARGET_SIGNAL_H */
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