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The Aspeed I2C controller maintains a state machine in the command register, which is mostly used for debug. Let's start adding a few states to handle abnormal STOP commands. Today, the model uses the busy status of the bus as a condition to do so but it is not precise enough. Also remove the ABNORMAL bit for failing TX commands. This is incorrect with respect to the specs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1494827476-1487-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| aspeed_i2c.c | ||
| bitbang_i2c.c | ||
| bitbang_i2c.h | ||
| core.c | ||
| exynos4210_i2c.c | ||
| i2c-ddc.c | ||
| imx_i2c.c | ||
| Makefile.objs | ||
| omap_i2c.c | ||
| pm_smbus.c | ||
| smbus_eeprom.c | ||
| smbus_ich9.c | ||
| smbus.c | ||
| versatile_i2c.c | ||