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Cathy Zhang 353f98c9ad x86/cpu: Enable AVX512_VP2INTERSECT cpu feature 
AVX512_VP2INTERSECT compute vector pair intersection to a pair
of mask registers, which is introduced with intel Tiger Lake,
defining as CPUID.(EAX=7,ECX=0):EDX[bit 08].

Refer to the following release spec:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Message-Id: <1586760758-13638-1-git-send-email-cathy.zhang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-06-10 12:10:27 -04:00
..
alpha
accel/tcg: Relax va restrictions on 64-bit guests
2020-05-15 15:25:16 +01:00
arm
target/arm: Convert Neon one-register-and-immediate insns to decodetree
2020-06-05 17:23:10 +01:00
cris
x86 and machine queue for 5.0 soft freeze
2020-03-19 14:22:46 +00:00
hppa
softfloat: Name compare relation enum
2020-05-19 08:41:45 -07:00
i386
x86/cpu: Enable AVX512_VP2INTERSECT cpu feature
2020-06-10 12:10:27 -04:00
lm32
x86 and machine queue for 5.0 soft freeze
2020-03-19 14:22:46 +00:00
m68k
target/m68k: implement opcode fetoxm1
2020-06-02 13:59:02 +02:00
microblaze
target/microblaze: monitor: Increase the number of registers reported
2020-05-14 16:01:02 +02:00
mips
target/mips: Support variable page size
2020-06-01 13:28:21 +02:00
moxie
cpu: Use DeviceClass reset instead of a special CPUClass reset
2020-03-17 19:48:10 -04:00
nios2
x86 and machine queue for 5.0 soft freeze
2020-03-19 14:22:46 +00:00
openrisc
softfloat: Name compare relation enum
2020-05-19 08:41:45 -07:00
ppc
target/ppc: Use tcg_gen_gvec_rotlv
2020-06-02 08:42:37 -07:00
riscv
linux-user pull request 20200605-v2
2020-06-08 11:04:57 +01:00
rx
target/rx/translate: Add missing fall through comment
2020-04-07 18:45:54 -07:00
s390x
linux-user pull request 20200605-v2
2020-06-08 11:04:57 +01:00
sh4
gdbstub: Introduce gdb_get_float32() to get 32-bit float registers
2020-04-15 11:38:23 +01:00
sparc
target/sparc/int32_helper: Extract and use excp_name_str()
2020-06-09 09:21:10 +02:00
tilegx
cpu: Use DeviceClass reset instead of a special CPUClass reset
2020-03-17 19:48:10 -04:00
tricore
target/tricore: Implement gdbstub
2020-06-01 16:55:13 +02:00
unicore32
softfloat: Name compare relation enum
2020-05-19 08:41:45 -07:00
xtensa
softfloat: Name compare relation enum
2020-05-19 08:41:45 -07:00