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xemu/trace-events
Stefan Hajnoczi eabba580e6 qed: Read/write support 
This patch implements the read/write state machine.  Operations are
fully asynchronous and multiple operations may be active at any time.

Allocating writes lock tables to ensure metadata updates do not
interfere with each other.  If two allocating writes need to update the
same L2 table they will run sequentially.  If two allocating writes need
to update different L2 tables they will run in parallel.

Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2010-12-17 16:11:04 +01:00

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# Trace events for debugging and performance instrumentation
#
# This file is processed by the tracetool script during the build.
#
# To add a new trace event:
#
# 1. Choose a name for the trace event. Declare its arguments and format
# string.
#
# 2. Call the trace event from code using trace_##name, e.g. multiwrite_cb() ->
# trace_multiwrite_cb(). The source file must #include "trace.h".
#
# Format of a trace event:
#
# [disable] <name>(<type1> <arg1>[, <type2> <arg2>] ...) "<format-string>"
#
# Example: qemu_malloc(size_t size) "size %zu"
#
# The "disable" keyword will build without the trace event.
# In case of 'simple' trace backend, it will allow the trace event to be
# compiled, but this would be turned off by default. It can be toggled on via
# the monitor.
#
# The <name> must be a valid as a C function name.
#
# Types should be standard C types. Use void * for pointers because the trace
# system may not have the necessary headers included.
#
# The <format-string> should be a sprintf()-compatible format string.
# qemu-malloc.c
disable qemu_malloc(size_t size, void *ptr) "size %zu ptr %p"
disable qemu_realloc(void *ptr, size_t size, void *newptr) "ptr %p size %zu newptr %p"
disable qemu_free(void *ptr) "ptr %p"
# osdep.c
disable qemu_memalign(size_t alignment, size_t size, void *ptr) "alignment %zu size %zu ptr %p"
disable qemu_vmalloc(size_t size, void *ptr) "size %zu ptr %p"
disable qemu_vfree(void *ptr) "ptr %p"
# hw/virtio.c
disable virtqueue_fill(void *vq, const void *elem, unsigned int len, unsigned int idx) "vq %p elem %p len %u idx %u"
disable virtqueue_flush(void *vq, unsigned int count) "vq %p count %u"
disable virtqueue_pop(void *vq, void *elem, unsigned int in_num, unsigned int out_num) "vq %p elem %p in_num %u out_num %u"
disable virtio_queue_notify(void *vdev, int n, void *vq) "vdev %p n %d vq %p"
disable virtio_irq(void *vq) "vq %p"
disable virtio_notify(void *vdev, void *vq) "vdev %p vq %p"
# block.c
disable multiwrite_cb(void *mcb, int ret) "mcb %p ret %d"
disable bdrv_aio_multiwrite(void *mcb, int num_callbacks, int num_reqs) "mcb %p num_callbacks %d num_reqs %d"
disable bdrv_aio_multiwrite_earlyfail(void *mcb) "mcb %p"
disable bdrv_aio_multiwrite_latefail(void *mcb, int i) "mcb %p i %d"
disable bdrv_aio_readv(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p"
disable bdrv_aio_writev(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p"
# hw/virtio-blk.c
disable virtio_blk_req_complete(void *req, int status) "req %p status %d"
disable virtio_blk_rw_complete(void *req, int ret) "req %p ret %d"
disable virtio_blk_handle_write(void *req, uint64_t sector, size_t nsectors) "req %p sector %"PRIu64" nsectors %zu"
# posix-aio-compat.c
disable paio_submit(void *acb, void *opaque, int64_t sector_num, int nb_sectors, int type) "acb %p opaque %p sector_num %"PRId64" nb_sectors %d type %d"
# ioport.c
disable cpu_in(unsigned int addr, unsigned int val) "addr %#x value %u"
disable cpu_out(unsigned int addr, unsigned int val) "addr %#x value %u"
# balloon.c
# Since requests are raised via monitor, not many tracepoints are needed.
disable balloon_event(void *opaque, unsigned long addr) "opaque %p addr %lu"
# hw/apic.c
disable apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d"
disable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t polarity, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d polarity %d trigger_mode %d"
disable cpu_set_apic_base(uint64_t val) "%016"PRIx64""
disable cpu_get_apic_base(uint64_t val) "%016"PRIx64""
disable apic_mem_readl(uint64_t addr, uint32_t val) "%"PRIx64" = %08x"
disable apic_mem_writel(uint64_t addr, uint32_t val) "%"PRIx64" = %08x"
# coalescing
disable apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d"
disable apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d"
disable apic_set_irq(int apic_irq_delivered) "coalescing %d"
# hw/cs4231.c
disable cs4231_mem_readl_dreg(uint32_t reg, uint32_t ret) "read dreg %d: 0x%02x"
disable cs4231_mem_readl_reg(uint32_t reg, uint32_t ret) "read reg %d: 0x%08x"
disable cs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x"
disable cs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x"
# hw/eccmemctl.c
disable ecc_mem_writel_mer(uint32_t val) "Write memory enable %08x"
disable ecc_mem_writel_mdr(uint32_t val) "Write memory delay %08x"
disable ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status %08x"
disable ecc_mem_writel_vcr(uint32_t val) "Write slot configuration %08x"
disable ecc_mem_writel_dr(uint32_t val) "Write diagnostic %08x"
disable ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 %08x"
disable ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 %08x"
disable ecc_mem_readl_mer(uint32_t ret) "Read memory enable %08x"
disable ecc_mem_readl_mdr(uint32_t ret) "Read memory delay %08x"
disable ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status %08x"
disable ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration %08x"
disable ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 %08x"
disable ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 %08x"
disable ecc_mem_readl_dr(uint32_t ret) "Read diagnostic %08x"
disable ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 %08x"
disable ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 %08x"
disable ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = %02x"
disable ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= %02x"
# hw/lance.c
disable lance_mem_readw(uint64_t addr, uint32_t ret) "addr=%"PRIx64"val=0x%04x"
disable lance_mem_writew(uint64_t addr, uint32_t val) "addr=%"PRIx64"val=0x%04x"
# hw/slavio_intctl.c
disable slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = %x"
disable slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = %x"
disable slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d irq mask %x, curmask %x"
disable slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq mask %x, curmask %x"
disable slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = %x"
disable slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) "write system reg 0x%"PRIx64" = %x"
disable slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask %x, curmask %x"
disable slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mask %x, curmask %x"
disable slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d"
disable slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) "pending %x disabled %x"
disable slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d"
disable slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d"
# hw/slavio_misc.c
disable slavio_misc_update_irq_raise(void) "Raise IRQ"
disable slavio_misc_update_irq_lower(void) "Lower IRQ"
disable slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d"
disable slavio_cfg_mem_writeb(uint32_t val) "Write config %02x"
disable slavio_cfg_mem_readb(uint32_t ret) "Read config %02x"
disable slavio_diag_mem_writeb(uint32_t val) "Write diag %02x"
disable slavio_diag_mem_readb(uint32_t ret) "Read diag %02x"
disable slavio_mdm_mem_writeb(uint32_t val) "Write modem control %02x"
disable slavio_mdm_mem_readb(uint32_t ret) "Read modem control %02x"
disable slavio_aux1_mem_writeb(uint32_t val) "Write aux1 %02x"
disable slavio_aux1_mem_readb(uint32_t ret) "Read aux1 %02x"
disable slavio_aux2_mem_writeb(uint32_t val) "Write aux2 %02x"
disable slavio_aux2_mem_readb(uint32_t ret) "Read aux2 %02x"
disable apc_mem_writeb(uint32_t val) "Write power management %02x"
disable apc_mem_readb(uint32_t ret) "Read power management %02x"
disable slavio_sysctrl_mem_writel(uint32_t val) "Write system control %08x"
disable slavio_sysctrl_mem_readl(uint32_t ret) "Read system control %08x"
disable slavio_led_mem_writew(uint32_t val) "Write diagnostic LED %04x"
disable slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED %04x"
# hw/slavio_timer.c
disable slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x"
disable slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x"
disable slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64""
disable slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x"
disable slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x"
disable slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64""
disable slavio_timer_mem_writel_counter_invalid(void) "not user timer"
disable slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started"
disable slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped"
disable slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer"
disable slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter"
disable slavio_timer_mem_writel_mode_invalid(void) "not system timer"
disable slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64""
# hw/sparc32_dma.c
disable ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64""
disable ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64""
disable sparc32_dma_set_irq_raise(void) "Raise IRQ"
disable sparc32_dma_set_irq_lower(void) "Lower IRQ"
disable espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x"
disable espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x"
disable sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x"
disable sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x"
disable sparc32_dma_enable_raise(void) "Raise DMA enable"
disable sparc32_dma_enable_lower(void) "Lower DMA enable"
# hw/sun4m.c
disable sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
disable sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
disable sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d"
disable sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d"
# hw/sun4m_iommu.c
disable sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x"
disable sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x"
disable sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64""
disable sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x"
disable sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x"
disable sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x"
disable sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x"
disable sun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64""
# vl.c
disable vm_state_notify(int running, int reason) "running %d reason %d"
# block/qed-l2-cache.c
disable qed_alloc_l2_cache_entry(void *l2_cache, void *entry) "l2_cache %p entry %p"
disable qed_unref_l2_cache_entry(void *entry, int ref) "entry %p ref %d"
disable qed_find_l2_cache_entry(void *l2_cache, void *entry, uint64_t offset, int ref) "l2_cache %p entry %p offset %"PRIu64" ref %d"
# block/qed-table.c
disable qed_read_table(void *s, uint64_t offset, void *table) "s %p offset %"PRIu64" table %p"
disable qed_read_table_cb(void *s, void *table, int ret) "s %p table %p ret %d"
disable qed_write_table(void *s, uint64_t offset, void *table, unsigned int index, unsigned int n) "s %p offset %"PRIu64" table %p index %u n %u"
disable qed_write_table_cb(void *s, void *table, int flush, int ret) "s %p table %p flush %d ret %d"
# block/qed.c
disable qed_aio_complete(void *s, void *acb, int ret) "s %p acb %p ret %d"
disable qed_aio_setup(void *s, void *acb, int64_t sector_num, int nb_sectors, void *opaque, int is_write) "s %p acb %p sector_num %"PRId64" nb_sectors %d opaque %p is_write %d"
disable qed_aio_next_io(void *s, void *acb, int ret, uint64_t cur_pos) "s %p acb %p ret %d cur_pos %"PRIu64""
disable qed_aio_read_data(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
disable qed_aio_write_data(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
disable qed_aio_write_prefill(void *s, void *acb, uint64_t start, size_t len, uint64_t offset) "s %p acb %p start %"PRIu64" len %zu offset %"PRIu64""
disable qed_aio_write_postfill(void *s, void *acb, uint64_t start, size_t len, uint64_t offset) "s %p acb %p start %"PRIu64" len %zu offset %"PRIu64""
disable qed_aio_write_main(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
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