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8c43a6f05d
Since 39bffca203 (qdev: register all
types natively through QEMU Object Model), TypeInfo as used in
the common, non-iterative pattern is no longer amended with information
and should therefore be const.
Fix the documented QOM examples:
sed -i 's/static TypeInfo/static const TypeInfo/g' include/qom/object.h
Since frequently the wrong examples are being copied by contributors of
new devices, fix all types in the tree:
sed -i 's/^static TypeInfo/static const TypeInfo/g' */*.c
sed -i 's/^static TypeInfo/static const TypeInfo/g' */*/*.c
This also avoids to piggy-back these changes onto real functional
changes or other refactorings.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
335 lines
10 KiB
C
335 lines
10 KiB
C
/*
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* Intel XScale PXA Programmable Interrupt Controller.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Copyright (c) 2006 Thorsten Zitterell
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GPL.
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*/
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#include "hw.h"
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#include "pxa.h"
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#include "sysbus.h"
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#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
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#define ICMR 0x04 /* Interrupt Controller Mask register */
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#define ICLR 0x08 /* Interrupt Controller Level register */
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#define ICFP 0x0c /* Interrupt Controller FIQ Pending register */
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#define ICPR 0x10 /* Interrupt Controller Pending register */
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#define ICCR 0x14 /* Interrupt Controller Control register */
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#define ICHP 0x18 /* Interrupt Controller Highest Priority register */
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#define IPR0 0x1c /* Interrupt Controller Priority register 0 */
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#define IPR31 0x98 /* Interrupt Controller Priority register 31 */
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#define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */
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#define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */
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#define ICLR2 0xa4 /* Interrupt Controller Level register 2 */
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#define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */
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#define ICPR2 0xac /* Interrupt Controller Pending register 2 */
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#define IPR32 0xb0 /* Interrupt Controller Priority register 32 */
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#define IPR39 0xcc /* Interrupt Controller Priority register 39 */
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#define PXA2XX_PIC_SRCS 40
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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ARMCPU *cpu;
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uint32_t int_enabled[2];
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uint32_t int_pending[2];
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uint32_t is_fiq[2];
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uint32_t int_idle;
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uint32_t priority[PXA2XX_PIC_SRCS];
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} PXA2xxPICState;
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static void pxa2xx_pic_update(void *opaque)
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{
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uint32_t mask[2];
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PXA2xxPICState *s = (PXA2xxPICState *) opaque;
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if (s->cpu->env.halted) {
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mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
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mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
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if (mask[0] || mask[1]) {
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cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
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}
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}
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mask[0] = s->int_pending[0] & s->int_enabled[0];
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mask[1] = s->int_pending[1] & s->int_enabled[1];
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if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
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cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
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} else {
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cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
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}
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if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
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cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
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}
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}
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/* Note: Here level means state of the signal on a pin, not
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* IRQ/FIQ distinction as in PXA Developer Manual. */
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static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque;
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int int_set = (irq >= 32);
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irq &= 31;
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if (level)
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s->int_pending[int_set] |= 1 << irq;
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else
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s->int_pending[int_set] &= ~(1 << irq);
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pxa2xx_pic_update(opaque);
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}
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static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
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int i, int_set, irq;
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uint32_t bit, mask[2];
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uint32_t ichp = 0x003f003f; /* Both IDs invalid */
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mask[0] = s->int_pending[0] & s->int_enabled[0];
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mask[1] = s->int_pending[1] & s->int_enabled[1];
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for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
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irq = s->priority[i] & 0x3f;
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if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) {
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/* Source peripheral ID is valid. */
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bit = 1 << (irq & 31);
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int_set = (irq >= 32);
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if (mask[int_set] & bit & s->is_fiq[int_set]) {
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/* FIQ asserted */
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ichp &= 0xffff0000;
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ichp |= (1 << 15) | irq;
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}
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if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
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/* IRQ asserted */
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ichp &= 0x0000ffff;
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ichp |= (1 << 31) | (irq << 16);
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}
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}
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}
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return ichp;
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}
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static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque;
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switch (offset) {
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case ICIP: /* IRQ Pending register */
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return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
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case ICIP2: /* IRQ Pending register 2 */
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return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
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case ICMR: /* Mask register */
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return s->int_enabled[0];
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case ICMR2: /* Mask register 2 */
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return s->int_enabled[1];
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case ICLR: /* Level register */
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return s->is_fiq[0];
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case ICLR2: /* Level register 2 */
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return s->is_fiq[1];
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case ICCR: /* Idle mask */
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return (s->int_idle == 0);
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case ICFP: /* FIQ Pending register */
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return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
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case ICFP2: /* FIQ Pending register 2 */
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return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
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case ICPR: /* Pending register */
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return s->int_pending[0];
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case ICPR2: /* Pending register 2 */
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return s->int_pending[1];
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case IPR0 ... IPR31:
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return s->priority[0 + ((offset - IPR0 ) >> 2)];
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case IPR32 ... IPR39:
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return s->priority[32 + ((offset - IPR32) >> 2)];
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case ICHP: /* Highest Priority register */
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return pxa2xx_pic_highest(s);
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default:
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printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
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return 0;
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}
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}
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static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque;
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switch (offset) {
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case ICMR: /* Mask register */
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s->int_enabled[0] = value;
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break;
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case ICMR2: /* Mask register 2 */
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s->int_enabled[1] = value;
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break;
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case ICLR: /* Level register */
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s->is_fiq[0] = value;
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break;
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case ICLR2: /* Level register 2 */
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s->is_fiq[1] = value;
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break;
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case ICCR: /* Idle mask */
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s->int_idle = (value & 1) ? 0 : ~0;
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break;
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case IPR0 ... IPR31:
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s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
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break;
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case IPR32 ... IPR39:
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s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
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break;
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default:
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printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
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return;
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}
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pxa2xx_pic_update(opaque);
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}
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/* Interrupt Controller Coprocessor Space Register Mapping */
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static const int pxa2xx_cp_reg_map[0x10] = {
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[0x0 ... 0xf] = -1,
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[0x0] = ICIP,
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[0x1] = ICMR,
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[0x2] = ICLR,
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[0x3] = ICFP,
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[0x4] = ICPR,
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[0x5] = ICHP,
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[0x6] = ICIP2,
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[0x7] = ICMR2,
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[0x8] = ICLR2,
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[0x9] = ICFP2,
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[0xa] = ICPR2,
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};
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static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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int offset = pxa2xx_cp_reg_map[ri->crn];
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*value = pxa2xx_pic_mem_read(ri->opaque, offset, 4);
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return 0;
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}
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static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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int offset = pxa2xx_cp_reg_map[ri->crn];
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pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
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return 0;
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}
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#define REGINFO_FOR_PIC_CP(NAME, CRN) \
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{ .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
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.access = PL1_RW, \
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.readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
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static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
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REGINFO_FOR_PIC_CP("ICIP", 0),
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REGINFO_FOR_PIC_CP("ICMR", 1),
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REGINFO_FOR_PIC_CP("ICLR", 2),
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REGINFO_FOR_PIC_CP("ICFP", 3),
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REGINFO_FOR_PIC_CP("ICPR", 4),
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REGINFO_FOR_PIC_CP("ICHP", 5),
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REGINFO_FOR_PIC_CP("ICIP2", 6),
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REGINFO_FOR_PIC_CP("ICMR2", 7),
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REGINFO_FOR_PIC_CP("ICLR2", 8),
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REGINFO_FOR_PIC_CP("ICFP2", 9),
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REGINFO_FOR_PIC_CP("ICPR2", 0xa),
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REGINFO_SENTINEL
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};
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static const MemoryRegionOps pxa2xx_pic_ops = {
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.read = pxa2xx_pic_mem_read,
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.write = pxa2xx_pic_mem_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int pxa2xx_pic_post_load(void *opaque, int version_id)
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{
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pxa2xx_pic_update(opaque);
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return 0;
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}
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DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
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{
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CPUARMState *env = &cpu->env;
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DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
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PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
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s->cpu = cpu;
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s->int_pending[0] = 0;
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s->int_pending[1] = 0;
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s->int_enabled[0] = 0;
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s->int_enabled[1] = 0;
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s->is_fiq[0] = 0;
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s->is_fiq[1] = 0;
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qdev_init_nofail(dev);
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qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
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/* Enable IC memory-mapped registers access. */
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memory_region_init_io(&s->iomem, &pxa2xx_pic_ops, s,
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"pxa2xx-pic", 0x00100000);
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sysbus_init_mmio(sysbus_from_qdev(dev), &s->iomem);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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/* Enable IC coprocessor access. */
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define_arm_cp_regs_with_opaque(arm_env_get_cpu(env), pxa_pic_cp_reginfo, s);
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return dev;
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}
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static VMStateDescription vmstate_pxa2xx_pic_regs = {
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.name = "pxa2xx_pic",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.post_load = pxa2xx_pic_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
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VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
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VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
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VMSTATE_UINT32(int_idle, PXA2xxPICState),
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VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
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VMSTATE_END_OF_LIST(),
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},
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};
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static int pxa2xx_pic_initfn(SysBusDevice *dev)
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{
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return 0;
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}
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static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = pxa2xx_pic_initfn;
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dc->desc = "PXA2xx PIC";
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dc->vmsd = &vmstate_pxa2xx_pic_regs;
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}
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static const TypeInfo pxa2xx_pic_info = {
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.name = "pxa2xx_pic",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PXA2xxPICState),
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.class_init = pxa2xx_pic_class_init,
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};
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static void pxa2xx_pic_register_types(void)
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{
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type_register_static(&pxa2xx_pic_info);
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}
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type_init(pxa2xx_pic_register_types)
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