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6c7c3c21f9
The new paging more is extension of IA32e mode with more additional page table level. It brings support of 57-bit vitrual address space (128PB) and 52-bit physical address space (4PB). The structure of new page table level is identical to pml4. The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16]. CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level paging mode. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Message-Id: <20161215001305.146807-1-kirill.shutemov@linux.intel.com> [Drop changes to target-i386/translate.c. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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| .. | ||
| arch_dump.c | ||
| arch_memory_mapping.c | ||
| bpt_helper.c | ||
| cc_helper_template.h | ||
| cc_helper.c | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| excp_helper.c | ||
| fpu_helper.c | ||
| gdbstub.c | ||
| helper.c | ||
| helper.h | ||
| hyperv.c | ||
| hyperv.h | ||
| int_helper.c | ||
| kvm_i386.h | ||
| kvm-stub.c | ||
| kvm.c | ||
| machine.c | ||
| Makefile.objs | ||
| mem_helper.c | ||
| misc_helper.c | ||
| monitor.c | ||
| mpx_helper.c | ||
| ops_sse_header.h | ||
| ops_sse.h | ||
| seg_helper.c | ||
| shift_helper_template.h | ||
| smm_helper.c | ||
| svm_helper.c | ||
| svm.h | ||
| TODO | ||
| trace-events | ||
| translate.c | ||