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2507c12ab0
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
216 lines
5.3 KiB
C
216 lines
5.3 KiB
C
/*
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* Intel XScale PXA255/270 PC Card and CompactFlash Interface.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GPLv2.
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*/
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#include "hw.h"
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#include "pcmcia.h"
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#include "pxa.h"
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struct PXA2xxPCMCIAState {
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PCMCIASocket slot;
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PCMCIACardState *card;
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qemu_irq irq;
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qemu_irq cd_irq;
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};
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static uint32_t pxa2xx_pcmcia_common_read(void *opaque,
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target_phys_addr_t offset)
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{
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
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if (s->slot.attached) {
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return s->card->common_read(s->card->state, offset);
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}
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return 0;
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}
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static void pxa2xx_pcmcia_common_write(void *opaque,
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target_phys_addr_t offset, uint32_t value)
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{
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
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if (s->slot.attached) {
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s->card->common_write(s->card->state, offset, value);
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}
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}
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static uint32_t pxa2xx_pcmcia_attr_read(void *opaque,
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target_phys_addr_t offset)
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{
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
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if (s->slot.attached) {
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return s->card->attr_read(s->card->state, offset);
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}
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return 0;
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}
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static void pxa2xx_pcmcia_attr_write(void *opaque,
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target_phys_addr_t offset, uint32_t value)
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{
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
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if (s->slot.attached) {
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s->card->attr_write(s->card->state, offset, value);
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}
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}
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static uint32_t pxa2xx_pcmcia_io_read(void *opaque,
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target_phys_addr_t offset)
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{
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
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if (s->slot.attached) {
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return s->card->io_read(s->card->state, offset);
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}
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return 0;
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}
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static void pxa2xx_pcmcia_io_write(void *opaque,
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target_phys_addr_t offset, uint32_t value)
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{
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
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if (s->slot.attached) {
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s->card->io_write(s->card->state, offset, value);
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}
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}
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static CPUReadMemoryFunc * const pxa2xx_pcmcia_common_readfn[] = {
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pxa2xx_pcmcia_common_read,
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pxa2xx_pcmcia_common_read,
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pxa2xx_pcmcia_common_read,
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};
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static CPUWriteMemoryFunc * const pxa2xx_pcmcia_common_writefn[] = {
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pxa2xx_pcmcia_common_write,
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pxa2xx_pcmcia_common_write,
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pxa2xx_pcmcia_common_write,
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};
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static CPUReadMemoryFunc * const pxa2xx_pcmcia_attr_readfn[] = {
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pxa2xx_pcmcia_attr_read,
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pxa2xx_pcmcia_attr_read,
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pxa2xx_pcmcia_attr_read,
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};
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static CPUWriteMemoryFunc * const pxa2xx_pcmcia_attr_writefn[] = {
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pxa2xx_pcmcia_attr_write,
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pxa2xx_pcmcia_attr_write,
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pxa2xx_pcmcia_attr_write,
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};
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static CPUReadMemoryFunc * const pxa2xx_pcmcia_io_readfn[] = {
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pxa2xx_pcmcia_io_read,
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pxa2xx_pcmcia_io_read,
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pxa2xx_pcmcia_io_read,
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};
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static CPUWriteMemoryFunc * const pxa2xx_pcmcia_io_writefn[] = {
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pxa2xx_pcmcia_io_write,
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pxa2xx_pcmcia_io_write,
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pxa2xx_pcmcia_io_write,
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};
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static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level)
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{
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
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if (!s->irq)
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return;
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qemu_set_irq(s->irq, level);
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}
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PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base)
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{
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int iomemtype;
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PXA2xxPCMCIAState *s;
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s = (PXA2xxPCMCIAState *)
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qemu_mallocz(sizeof(PXA2xxPCMCIAState));
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/* Socket I/O Memory Space */
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iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_io_readfn,
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pxa2xx_pcmcia_io_writefn, s, DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype);
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/* Then next 64 MB is reserved */
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/* Socket Attribute Memory Space */
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iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_attr_readfn,
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pxa2xx_pcmcia_attr_writefn, s, DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype);
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/* Socket Common Memory Space */
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iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_common_readfn,
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pxa2xx_pcmcia_common_writefn, s, DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype);
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if (base == 0x30000000)
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s->slot.slot_string = "PXA PC Card Socket 1";
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else
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s->slot.slot_string = "PXA PC Card Socket 0";
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s->slot.irq = qemu_allocate_irqs(pxa2xx_pcmcia_set_irq, s, 1)[0];
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pcmcia_socket_register(&s->slot);
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return s;
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}
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/* Insert a new card into a slot */
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int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card)
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{
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
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if (s->slot.attached)
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return -EEXIST;
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if (s->cd_irq) {
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qemu_irq_raise(s->cd_irq);
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}
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s->card = card;
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s->slot.attached = 1;
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s->card->slot = &s->slot;
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s->card->attach(s->card->state);
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return 0;
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}
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/* Eject card from the slot */
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int pxa2xx_pcmcia_dettach(void *opaque)
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{
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
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if (!s->slot.attached)
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return -ENOENT;
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s->card->detach(s->card->state);
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s->card->slot = NULL;
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s->card = NULL;
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s->slot.attached = 0;
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if (s->irq)
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qemu_irq_lower(s->irq);
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if (s->cd_irq)
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qemu_irq_lower(s->cd_irq);
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return 0;
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}
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/* Who to notify on card events */
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void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq)
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{
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
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s->irq = irq;
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s->cd_irq = cd_irq;
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}
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